SLVS753C February   2007  – November 2016 TPS40180


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Sensing and Overcurrent Detection
      2. 7.3.2 Hiccup Fault Recovery
      3. 7.3.3 Selecting Current Sense Network Components
      4. 7.3.4 PGOOD Functionality
      5. 7.3.5 Output Overvoltage and Undervoltage Protection
      6. 7.3.6 Overtemperature Protection
      7. 7.3.7 eTRIM™
      8. 7.3.8 Connections Between Controllers for Stacking
      9. 7.3.9 VSH Line in the Multiphase
    4. 7.4 Device Functional Modes
      1. 7.4.1 Tracking
    5. 7.5 Programming
      1. 7.5.1 Programming the Operating Frequency
      2. 7.5.2 Programming the Soft-Start Time
      3. 7.5.3 Using the Device for Clock Master/Slave Operation
      4. 7.5.4 Using the TPS40180 for Voltage Control Loop Master or Slave Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Single Output Synchronous Buck Converter
        1. Design Requirements
        2. Detailed Design Procedure
          1. Inductor Selection
          2. Output Capacitor Selection
          3. Input Capacitor Selection
          4. MOSFET Selection
          5. Peripheral Component Design
            1.  Switching Frequency Setting (RT)
            2.  Output Voltage Setting (FB)
            3.  Current Sensing Network Design (CS+, CS-)
            4.  Overcurrent Protection (ILIM)
            5.  VREG (PVCC)
            6.  BP5
            7.  Phase Select (PSEL)
            8.  VSHARE (VSH)
            9.  Powergood (PGOOD)
            10. Undervoltage Lockout (UVLO)
            11. Clock Synchronization (CLKIO)
            12. Bootstrap Capacitor
            13. Soft Start (SS)
            14. Remote Sense
            15. Feedback Compensator Design
        3. Application Curves
      2. 8.2.2 Simultaneous Tracking With TPS40180 Devices
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 8.2.3 2-Phase Single Output With TPS40180
        1. Design Requirements
        2. Detailed Design Procedure
          1. Inductor Selection
          2. Output Capacitor Selection
          3. Input Capacitor Selection
          4. Peripheral Component Design
            1. PSEL Pin
            2. CLKIO Pin
            3. RT Pin
            4. SS Pin
            5. DIFFO Pin and FB Pin
            6. COMP Pin
            7. VSH Pin
            8. Other Pins
        3. Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Stage
      2. 10.1.2 Device Peripheral
      3. 10.1.3 PowerPad Layout™
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

Power Stage

A synchronous BUCK power stage has two primary current loops. One is the input current loop which carries high AC discontinuous current adn the other is the output current loop carrying a high DC continuous current.

The input current loop includes the input capacitors, the main switching MOSFET, the inductor, the output capacitors and the ground path back to the input capacitors. To keep this loop as small as possible, it is generally good practice to place some ceramic capacitance directly between the drain of the main switching MOSFET and the source of the synchronous rectifier (SR) through a power ground plane directly under the MOSFETs.

The output current loop includes the SR MOSFET, the inductor, the output capacitors, and the ground return between the output capacitors and the source of the SR MOSFET. As with the input current loop, the ground return between the output capacitor ground and the source of the SR MOSFET should be routed under the inductor and SR MOSFET to minimize the power loop area.

The SW node area should be as small as possible to reduce the parasitic capacitance and minimize the radiated emissions.

The gate drive loop impedance (HDRV-gate-source-SW and LDRV-gate-source-GND) should be kept to as low as possible. The HDRV and LDRV connections should widen to 20 mils as soon as possible out from the IC pin.

Device Peripheral

The TPS40180 provides separate signal ground (GND) and power ground (PGND) pins. It is required to separate properly the circuit grounds. The return path for the pins associated with the power stage should be through PGND. The other pins especially for those sensitive pins such as FB, RT and ILIM should be through the low noise GND. The GND and PGND plane are suggested to be connected at the output capacitor with single 20 mil trace.

A minimum 0.1-µF ceramic capacitor must be placed as close to the VDD pin and AGND as possible with at least 15-mil wide trace from the bypass capacitor to the GND.

A 4.7-µF ceramic capacitor should be placed as close to the PVCC pin and PGND as possible.

BP5 is the filtered input from the PVCC pin. A 4.7-Ω resistor should be connected between PVCC and BP5 and a 1-µF ceramic capacitor should be connected from BP5 to GND. Both components should be as close to BP5 pin as possible.

When a DCR sensing method is applied, the sensing resistor is placed close to the SW node. It is connected to the inductor with Kelvin connection. The sensing traces from the power stage to the chip should be away from the switching components. The sensing capacitor should be placed very close to the CS+ and CS– pins. The frequency setting resistor should be placed as close to RT pin and GND as possible. The VOUT and GSNS pins should be directly connected to the point of load where the voltage regulation is required.

A parallel pair of 10-mil traces connects the regulated voltage back to the chip. They should be away from the switching components. The PowerPAD should be electrically connected to GND.

PowerPad Layout™

The PowerPAD™ package provides low thermal impedance for heat removal from the device. The PowerPAD™ derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend on the size of the PowerPAD™ package. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter plus 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD™ Thermally Enhanced Package for more information on the PowerPAD™ package.

Layout Example

TPS40180 TPS40180_recommended_layout_peripheral_components_slvs753.gif Figure 42. TPS40180 Recommended Layout for Peripheral Components
TPS40180 TPS40180_peripheral_schematic_slvs753.gif Figure 43. TPS40180 Peripheral Schematic