SLVS753 Data sheet

SLVS753C February 2007 – November 2016 TPS40180

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RGE|24
- MPQF124G

Thermal pad, mechanical data (Package|Pins)

RGE|24
- QFND008AA

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Input voltage, V_I	VDD, UVLO, RT, SS	–0.3	16	V
Input voltage, V_I	FB, VOUT, GSNS, VSH, ILIM, BP5, PSEL, CS+, CS–, VS+, VS–	–0.3	6	V
Output voltage, V_O	BOOT – HDRV	–0.3	6	V
	SW, HDRV	–1	44
	SW, HDRV, transient (<50 ns)	–5	44
	DIFFO, LDRV, PVCC, CLKIO, PGOOD, COMP	–0.3	6
	PGOOD (eTrim™ usage only)	–0.3	22
Operating junction temperature, T_J		–40	150	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_I	Input voltage	VDD, UVLO	4.5		15	V
		SW	–1		40
		BOOT – SW		5.5
		All other pins	0		5.8
	RT				25	µA
	PSEL				150	µA
T_J	Operating junction temperature		–40		105	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS40180	UNIT
		RGE (VQFN)
		24 PINS
R_θJA	Junction-to-ambient thermal resistance	33.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	34.4	°C/W
R_θJB	Junction-to-board thermal resistance	11.6	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	11.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

V_VDD = 12 V, V_BP5 = 15 V, V_PVCC = 5 V, –40°C ≤ T_J ≤ 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VDD INPUT SUPPLY
V_VDD	Operating voltage range		4.5	12	15	V
I_VDDSD	Shutdown current	V_UVLO < 0.5 V			50	µA
BP5 INPUT SUPPLY
V_BP5	Operating voltage range		4.3	5	5.5	V
I_BP5	Operating current		2	3	5	mA
V_BP5UV	Rising undervoltage turn on threshold		4	4.25	4.5	V
V_BP5UVH	BP5 UVLO hysteresis			225		mV
PVCC REGULATOR
V_PVCC	Output voltage	4.5 V < V_DD < 15 V	4.3	5	5.5	V
I_PVCC	Output current		0		50	mA
OSCILLATOR
F_OSC	Oscillator frequency	R_RT = 64.9 kΩ	360	415	454	kHz
F_OSC	Oscillator frequency range		150		1000	kHz
V_RMP	Ramp voltage⁽¹⁾		420	500	525	mV
V_RTCKLSLV	RT pin clock slave voltage threshold				2	V
DIGITAL CLOCK SIGNAL (CLKIO)
R_CLKH	Pull up resistance⁽¹⁾			27		Ω
R_CLKL	Pull down resistance⁽¹⁾			27		Ω
I_CLKIOLK	Leakage current in high impedance state⁽¹⁾	V_RT < 2 V, V_PSEL = 5 V			1	µA
UVLO PIN
V_UVLO(on)	PVCC regulator enabled		0.8	0.9	1.5	V
V_UVLO(on)	PWM switching enabled		1.9	2	2.1	V
I_UVLO	Hysteresis bias current		9	12	15	µA
PULSE WIDTH MODULATOR
D_MAX	Maximum duty cycle	8 phase CLK scheme		87.5%
D_MAX	Maximum duty cycle	6 phase CLK scheme		83%
t_ON(min)	Minimum pulse width⁽¹⁾			75		ns
VSHARE
V_VSH	Current share reference; ramp valley voltage	R_LOAD = 20 kΩ	1.7	1.8	1.9	V
ERROR AMPLIFIER
I_IB	Input bias current at FB pin	V_FB = 0.7 V	–200	0	200	nA
V_REF	Trimmed FB control voltage	Includes differential sense amp offset	695	700	705	mV
I_OH	COMP source current	V_COMP = 1.1 V, V_FB = 0.6 V	1	2		mA
I_OL	COMP sink current	V_COMP = 1.1 V, V_FB = 0.8 V	1	2		mA
EA_GBWP	Gain bandwidth product⁽¹⁾		8	12		MHz
A_OL	Open loop gain⁽¹⁾		60	90		dB
SOFTSTART
I_SS1	Charging current (before first PWM pulse)	Device enabled, during hiccup fault recovery	6.5	7.5	8.2	µA
I_SS2	Charging current (after first PWM pulse)		12	15	17	µA
V_{SS_FE}	Fault enable threshold			0.8		V
V_SSSLV	Voltage loop slave mode threshold voltage	V_BP5 = 5 V			V_BP5 – 0.75	V
CURRENT LIMIT
I_ILIM	Threshold setting current		21.5	23.5	25.5	µA
CURRENT SENSE AMPLIFIER
V_ISOFST	Input offset voltage		–2.5	0	2.5	mV
I_{IS_CS}	Input bias current			100		nA
G_CS	Gain at PWM input	0.2 V ≤ V_ICM ≤ 5.8 V	11.25	12.5	13.75	V/V
V_ICM	Input common mode range		0		5.8	V
V_DIFFMX	Maximum differential input voltage		–60		60	mV
DIFFERENTIAL REMOVE VOLTAGE SENSE AMPLIFIER
GRVS	Gain	0.7 V < V_(VOUT) – V_(GSNS) < 5.8 V	0.995	1	1.005	V/V
I_DIFFOH	DIFFO source current	V_(VOUT) – V_(GSNS) = 2 V, V_(DIFFO) > 1.98 V, V_(VDD) – V_(VOUT) > 2 V			2	mA
I_DIFFOH	DIFFO source current	V_(VOUT) – V_(GSNS) = 5.8 V, V_(DIFFO) > 5.6 V, V_(VDD) – V_(VOUT) > 1 V			1	mA
I_DIFFOL	DIFFO sink current	V_(VOUT) – V_(GSNS) = 2 V, V_(DIFFO) > 2.02 V			2	mA
BW_DIFFA	Unity gain bandwidth⁽¹⁾		5	8		MHz
R_INDIFFA	Input resistance	Inverting, DIFFO to GSNS		60		kΩ
R_INDIFFA	Input resistance	Noninverting, OUT to GND		60		kΩ
PSEL PIN
I_ISEL	Bias current		21.5	23.5	25.5	µA
V_MNCLK	Master mode	No output on CLKIO	0	0	0.5	V
V_M8PH		8 phase CLKIO	0.5	0.7	0.9
V_M6PH		6 phase CLKIO	0.9
V_SSTDBY	Slave mode, standby state		3.4			V
V_S45	Clock slave mode, 45° phase slot⁽¹⁾	8 phase CLKIO	0	0	0.2	V
V_S90	Clock slave mode, 90° phase slot⁽¹⁾	8 phase CLKIO	0.2	0.35	0.5	V
V_S135	Clock slave mode, 135° phase slot⁽¹⁾	8 phase CLKIO	0.5	0.7	0.9	V
V_S180	Clock slave mode, 180° phase slot⁽¹⁾	8 phase CLKIO	0.9	1.1	1.3	V
V_S225	Clock slave mode, 225° phase slot⁽¹⁾	8 phase CLKIO	1.3	1.6	1.9	V
V_S270	Clock slave mode, 270° phase slot⁽¹⁾	8 phase CLKIO	1.9	2.25	2.6	V
V_S315	Clock slave mode, 315° phase slot⁽¹⁾	8 phase CLKIO	2.6	3	3.4	V
V_S0	Clock slave mode, 0 phase slot⁽¹⁾	6 phase CLKIO	1.9	2.25	2.6	V
V_S60	Clock slave mode, 60° phase slot⁽¹⁾	6 phase CLKIO	0	0	0.2	V
V_S120	Clock slave mode, 120° phase slot⁽¹⁾	6 phase CLKIO	0.2	0.35	0.5	V
V_S180	Clock slave mode, 180° phase slot⁽¹⁾	6 phase CLKIO	0.5	0.7	0.9	V
V_S240	Clock slave mode, 240° phase slot⁽¹⁾	6 phase CLKIO	0.9	1.1	1.3	V
V_S300	Clock slave mode, 300° phase slot⁽¹⁾	6 phase CLKIO	1.3	1.6	1.9	V
GATE DRIVERS
R_HDRV(on)	HDRV pull up resistance	V_BOOT = 5 V, V_(SW) = 0 V, I_HDRV = 100 mA	1	2	3	Ω
R_HDRV(off)	HDRV pull down resistance	V_BOOT = 5 V, V_(SW) = 0 V, I_HDRV = 100 mA	0.5	1	2	Ω
R_LDRV(on)	LDRV pull up resistance	V_PVCC = 5 V, I_LDRV = 100 mA	1	2	3.5	Ω
R_LDRV(off)	LDRV pull down resistance	V_PVCC = 5 V, I_LDRV = 100 mA	0.3	0.75	1.5	Ω
t_HDRV(r)	HDRV rise time⁽¹⁾	C_LOAD = 3.3 nF		25	75	ns
t_HDRV(f)	HDRV fall time⁽¹⁾	C_LOAD = 3.3 nF		25	75	ns
t_LDRV(r)	LDRV rise time⁽¹⁾	C_LOAD = 3.3 nF		25	75	ns
t_LDRV(f)	LDRV fall time⁽¹⁾	C_LOAD = 3.3 nF		10	60	ns
POWER GOOD
V_{FBPG_H}	Power good high FB voltage threshold		764	787	798	mV
V_{FBPG_L}	Power good low FB voltage threshold		591	611	626	mV
V_FBPG(hyst)	Power good threshold hysteresis		30		60	mV
T_PGDLY	Power good delay time⁽¹⁾			10		µs
V_PGL	Power good low level output voltage	I_PG = 2 mA		0.35	0.4	V
I_PGLK	Power good leakage current	V_PG = 5 V		1		µA
OVERVOLTAGE AND UNDERVOLTAGE
V_{FB_U}	FB pin under voltage threshold		565	580	595	mV
V_{FB_O}	FB pin over voltage threshold		792	810	828	mV
THERMAL SHUTDOWN
T_TSD	Shutdown temperature⁽¹⁾		126	135	144	°C
T_TSD(hyst)	Hysteresis⁽¹⁾			40		°C
T_WRN	Warning temperature⁽¹⁾		106	115	124	°C
T_WR(hyst)	Hysteresis⁽¹⁾			10		°C