Table 1. Design Parameters

8.2.1.2.1 FET Selection Criteria

1. The maximum input voltage for this application is 16 V. Switching the inductor causes overshoot voltages that can equal the input voltage. Because the R_DS(on) of the FET rises with breakdown voltage, select a FET with the lowest breakdown voltage possible. In this case, a 30-V FET was selected.
2. Selecting the size of a power FET requires knowing both the switching losses and DC losses in the application. AC losses are all frequency dependent and directly related to device capacitances and device size. However, DC losses are inversely related to device size. The result is an optimum where the two types of losses are equal. Because device size is proportional to R_DS(on), begin by selecting a device with an R_DS(on) that results in a small loss of power relative to package thermal capability and overall efficiency objectives.
3. In this application, the efficiency target is 90% and the output power 8.25 W. This gives a total power-loss budget of 0.916 W. Total FET losses must be small relative to this number.

The DC conduction loss in the FET is given by Equation 8.

The RMS current is given by Equation 9.

Equation 9.

where

• ΔI_pp = ΔV × D × (t_s/L_I)
• ΔV = V_IN – V_OUT – (DCR + R_DS(on)) × I_OUT
• R_DS(on) = FET on-state resistance
• DCR = inductor DC resistance
• D = duty cycle
• t_S = reciprocal of the switching frequency

Using the values in this example, the DC power loss is 129 mW. The remaining FET losses are as follows:

• P_SW – The power dissipated while switching the FET on and off
• P_GATE – The power dissipated driving the FET gate capacitance
• P_COSS – The power switching the FET output capacitance

The total power dissipated by the FET is calculated using Equation 10.

The P-channel FET, Q2, used in this application is a FDC654P with the following characteristics:

• t_RISE = 13 × 10^–9
• t_FALL = 6 × 10^–9
• R_DS(on) = 0.1 Ω
• Q_GD = 1.2 × 10^–9
• C_OSS = 83 × 10^–12
• Q_G = 9 nC
• V_GATE = 1.9 V
• Q_GS = 1 × 10^–9

Using these device characteristics and the following formulas, P_SW is calculated using Equation 11:

Equation 11.

where

Equation 12.

Equation 13.

The gate current is I_G = Q_G × f_S = 2.7 mA.

The sum of the switching losses is 34 mW and is comparable to the 129-mW DC losses. At added expense, a slightly larger FET is better, because the DC loss drops and the AC losses increase, with both moving toward the optimum point of equal losses.

8.2.1.2.2 Rectifier Selection Criteria

• Rectifier breakdown voltage:

The rectifier must withstand the maximum input voltage, which in this case is 16 V. To allow for switching transients that can approach the switching voltage, a 30-V rectifier was selected.

• Diode size:

The importance of power losses from the Schottky rectifier (D2) is determined by the duty cycle. For a low duty-cycle application, the rectifier conducts most of the time and the current that flows through it times its forward drop can be the largest component of loss in the entire controller. In this application, the duty cycle ranges from 20% to 40%, which in the worst case means that the diode conducts 80% of the time. Where efficiency is of paramount importance, choose a diode with a minimum forward drop. In more cost-sensitive applications, size may be reduced to the point of the thermal limitations of the diode package.

The device in this application is large relative to the current required by the application. In a more cost-sensitive application, a smaller diode in a less-expensive package will provide a less-efficient but appropriate solution.

The device used, D2, has the following characteristics:

• V_f = 0.3 V at 3 A
• C_t = 300 pF (C_t = effective reverse voltage capacitance of the synchronous rectifier, D2)

The two components of the losses from the diode D2 are calculated using Equation 14.

Equation 14.
where
• D = duty cycle
• I_RIPPLE = ripple current
• I_OUT = output current
• V_F = forward voltage
• P_COND = conduction power loss

The switching capacitance of this diode adds an AC loss, given by Equation 15.

Equation 15.

This additional loss raises the total loss to 660 mW.


At an output voltage of 3.3 V, the application runs at a nominal duty cycle of 27% with the diode conducting 72.5% of the time. As the output voltage is moved up to 5 V, the on time increases to 46% with the diode conducting only 54% of the time during each clock cycle. This change in duty cycle proportionately reduces the conduction power losses in the diode. This reduction may be expressed as Equation 16.

Equation 16.

for a savings in power of 660 – 491 = 169 mW.


To illustrate the relevance of this power savings, measure the full-load module efficiency for this application at 3.3 V and 5 V. The 5-V output efficiency is 92% versus 89% for the 3.3-V design. This difference in efficiency represents a 456-mW reduction in loss between the two conditions. This 169-mW power-loss reduction in the rectifier represents 37% of the difference.

8.2.1.2.3 Inductor Selection Criteria

The TPS40200-Q1 P-FET driver facilitates switching the power FET at a high frequency. In turn, this enables the use of smaller less-expensive inductors as illustrated in this 300-kHz application. Ferrite, with its good high-frequency properties, is the material of choice. Several manufacturers provide catalogs with inductor saturation currents, inductance values, and LSRs (internal resistance) for their various-sized ferrites.

In this application, the device must deliver a maximum current of 2.5 A. This requires that the saturation current of the output inductor is above 2.5 A plus one-half the ripple current caused during inductor switching. The value of the inductor determines this ripple current. A low value of inductance has a higher ripple current that contributes to ripple voltage across the resistance of the output capacitors. The advantages of a low inductance are a higher transient response, lower DCR, a higher saturation current, and a smaller less-expensive device. Too low an inductor, however, leads to higher peak currents, which ultimately are bounded by the overcurrent limit set to protect the output FET or by output ripple voltage. Fortunately, with low-ESR ceramic capacitors on the output, the resulting ripple voltage for relatively high ripple currents can be small.

For example, a single 1-μF 1206-sized 6.3-V ceramic capacitor has an internal resistance of 2 Ω at 1 MHz. For this 2.5-A application, a 10% ripple current of 0.25 A produces a 50-mV ripple voltage. This ripple voltage may be further reduced by additional parallel capacitors.

The other bound on inductance is the minimum current at which the controller enters discontinuous conduction. At this point, inductor current is zero. The minimum output current for this application is specified at 0.125 A. This average current is one-half the peak current that must develop during a minimum on time. The conditions for minimum on time are high line and low load.

L_MIN is calculated using Equation 17.

Equation 17.

where

• V_IN = 16 V
• V_OUT = 3.3 V
• I_PEAK = 0.25 A
• t_ON = 0.686 μs
• t_ON is given by

The inductor used in the circuit, L1, is the closest standard value of 33 μH. This is the minimum inductance that can be used in the converter to deliver the minimum current while maintaining continuous conduction.

8.2.1.2.4 Output Capacitance

In order to satisfy the output voltage overshoot and undershoot specifications, there must be enough output capacitance to keep the output voltage within the specified voltage limits during load current steps.

In a situation where a full load of 2.5 A within the specified voltage limits is suddenly removed, the output capacitor must absorb energy stored in the output inductor. This condition may be described by realizing that the energy in the stored in the inductor must be suddenly absorbed by the output capacitance. This energy relationship is written using Equation 18.

Equation 18.

where

• V_OS = allowed overshoot voltage above the output voltage
• L_O = inductance
• I_O = output current
• C_O = output capacitance
• V_O = output voltage

In this application, the worst-case load step is 2.25 A, and the allowed overshoot is 100 mV. With a 33-μH output inductor, this implies an output capacitance of 249 μF for a 3.3-V output and 165 μF for a 5-V output.

When the load increases from minimum to full load, the output capacitor must deliver current to the load. The worst case is for a minimum on time that occurs at 16 V_IN, 3.3 V_OUT, and minimum load. This corresponds to an off time of (1 – 0.2) times the period 3.3 μs and is the worst-case time before the inductor can start supplying current. This situation may be represented using Equation 19.

Equation 19.

where

• ΔV_O = undershoot specification of 60 mV
• ΔI_O = load current step
• t_OFFMAX = maximum off time

This condition produces a requirement of 100 μF for the output capacitance. The larger of these two requirements becomes the minimum value of output capacitance. In the schematic, an output capacitor of 220 µF (C12) in parallel with 1 µF (C11) is shown. This is from the EVM to balance both 3.3-V and 5-V output use cases. For fixed voltage output, modify the C11 and C12 values per the equations.

The ripple current develops a voltage across the ESR of the output capacitance, so another requirement on this component is that ESR be small relative to the ripple voltage specification.

8.2.1.2.5 Switching Frequency

The TPS40200-Q1 has a built-in 8-V, 200-mA, P-channel FET-driver output that facilitates using P-channel switching FETs. A clock frequency of 300 kHz was chosen as a switching frequency that represents a compromise between a high frequency that allows the use of smaller capacitors and inductors, and one that is not so high as to cause excessive transistor switching losses. As previously discussed, an optimum frequency can be selected by picking a value where the DC and switching losses are equal.

The frequency is set by using the design formula given in FET Selection Criteria.

Equation 20.

where

• R_RC = timing resistor value in Ω or R3 = 68.1 kΩ
• C_RC = timing capacitor value in F or C5 = 470 pF
• f_SW = desired switching frequency in Hz, which in this case is 297 kHz

At a worst case of 16 V, the timing resistor draws about 250 μA, which is well below the 750-μA maximum that the circuit can pull down.

8.2.1.2.6 Calculating the Overcurrent Threshold Level

The current limit in the TSP40200-Q1 is triggered by a comparator with a 100-mV offset whose inputs are connected across a current-sense resistor between V_DD and the source of the high-side switching FET. When current in this resistor develops more than 100 mV, the comparator trips and terminates the output gate drive.

In this application, the current-limit resistor is set by the peak output stage current, which consists of the maximum load current plus one-half the ripple current. In this case, 2.5 + 0.125 = 2.625 A. To accommodate tolerances, a 25% margin is added, giving a 3.25-A peak current. Using the equation for I_ILIM, Figure 32 yields a value for R_ILIM of 31 mΩ. In the schematic, a 20-mΩ resistor, R2, was used for R_ILIM, which sets the current limit to 5 A. This schematic is from the EVM where evaluation at a higher current was allowed.

Current sensing in a switching environment requires attention to both circuit board traces and noise pickup. In the design shown, a small RC filter has been added to the circuit to prevent switching noise from tripping the current-sense comparator. The requirements of this filter are board dependent, but with the layout used in this application, no spurious overcurrent is observed.

Figure 32. Overcurrent Trip Circuit for R_F2 Open

8.2.1.2.7 Soft-Start Capacitor

The soft-start interval is given (in pF) by Equation 21.

Equation 21.

where

• R = internal 105-kΩ charging resistor
• V_CC = input voltage up to 8 V, where the charging voltage is internally clamped to 8 V maximum
• V_OS = 700 mV, and (because the input voltage is 12 V) V_SST = 8 V

The oscilloscope (Figure 33) shows the expected delay at the output (middle trace) until the soft-start node (bottom trace) reaches 700 mV. At this point, the output rises following the exponential rise of the soft-start capacitor voltage until the soft-start capacitor reaches 1.4 V and the internal 700-mV reference takes over. This total time is approximately 1 ms, which agrees with the calculated value of 0.95 ms when the soft-start capacitance is 0.047 μF, C6.

A. Channel 1 is the output voltage rising to 3.3 V.

B. Channel 2 is the soft-start pin.

Figure 33. Soft Start Showing Output Delay and Controlled Rise to Programmed Output Voltage

8.2.1.2.8 Frequency Compensation

The four elements that determine the system overall response are discussed in this section. The gain of the error amplifier (K_EA) is the first of these elements. Its output develops a control voltage that is the input to the PWM.

The TPS40200-Q1 has a unique modulator that scales the peak-to-peak amplitude of the PWM ramp to be 0.1 times the value of the input voltage. Because modulator gain is given by V_IN divided by V_RAMP, the modulator gain is 10 and is constant at 10 (20 dB) over the entire specified input-voltage range.

The last two elements that affect system gain are the transfer characteristic of the output LC filter and the feedback network from the output to the input to the error amplifier.

These four elements may be expressed using Equation 22 that represents the system transfer function as shown in Figure 34.

Equation 22. T_V(S) = K_FB × K_EA(S) × K_PWM × X_LC(S)

where

• K_FB = output voltage setting divider
• K_EA = error amplifier feedback
• K_PWM = modulator gain
• X_LC = filter transfer function

Figure 34. Control Loop

Figure 35 shows the feedback network used in this application. This is a Type II compensation network, which gives a combination of good transient response and phase boost for good stability. This type of compensation has a pole at the origin, causing a –20-dB/decade (–1) slope, followed by a zero that causes a region of flat gain, followed by a final pole that returns the gain slope to –1. The Bode plot in Figure 36 shows the effect of these poles and zeros.

The procedure for setting up the compensation network is as follows:

1. Determine the break frequency of the output capacitor.
2. Select a zero frequency well below this break frequency.
3. From the gain bandwidth of the error amplifier, select a crossover frequency at which the amplifier gain is large relative to expected closed-loop gain.
4. Select a second zero well above the crossover frequency that returns the gain slope to a –1 slope.
5. Calculate the required gain for the amplifier at crossover.

Figure 35. Error Amplifier Feedback Elements

The frequency response of this converter is largely determined by two poles that arise from the LC output filter and a higher-frequency zero caused by the ESR of the output capacitance. The poles from the output filter cause a 40-dB/decade rolloff with a phase shift approaching 180 degrees, followed by the output capacitor zero that reduces the roll off to –20 dB and gives a phase boost back toward 90 degrees. In other nomenclature, this is a –2 slope followed by a –1 slope. The two zeros in the compensation network act to cancel the double pole from the output filter. The two poles of the compensation network produce a region in which the error amplifier is flat and can be set to a gain such that the overall gain of the system is 0 dB. This region is set so that it brackets the system crossover frequency.

Figure 36. Error Amplifier Bode Plot

To properly compensate this system, it is necessary to know the frequencies of its poles and zeros.

8.2.1.2.8.1 Step 1

The break frequency of the output capacitor is given by Equation 23.

Equation 23.

where

• C_OUT = the output capacitor
• R_ESR = the ESR of the capacitors

Because of the ESR of the output capacitor, this output filter has a single-pole response above the 1.8-kHz break frequency of the output capacitor and its ESR. This simplifies compensation since the system becomes essentially a single-pole system.

8.2.1.2.8.2 Step 2

The first zero is placed well below the 1.8-kHz break frequency of the output capacitor and its ESR. Phase boost from this zero is shown in Figure 38.

Equation 24.

where

• R₈ = 300 kΩ
• C₈ = 1500 pF
• f_Z1 = 354 Hz

8.2.1.2.8.4 Step 4

The second pole is placed well above the 35-kHz crossover frequency.

Equation 25.

where

• R₈ = 300 kΩ
• C₇ = 10 pF
• C₈ = 1500 pF
• f_P2 = 53 kHz

8.2.1.2.8.5 Step 5

Use Equation 26 to calculate the gain elements in the system to determine the gain required by the error amplifier to make the overall gain 0 dB at 35 kHz.

Equation 26.

where

• K_FB is the output voltage setting divider
• K_EA is the error amplifier feedback
• K_PWM is the modulator gain
• X_LC is the filter transfer function

With reference to Figure 37, the transfer characteristic X_LC(S) of the output filter can be estimated by Equation 27.

Figure 37. Output Filter Analysis

Equation 27.

where

• Z_OUT is the parallel combination of output capacitor(s) and the load
• R_SW is the R_DS(on) of the switching FET plus the current-sense resistor
• R_SR is the resistance of the synchronous rectifier
• D is the duty cycle estimated as 3.3 / 12 = 0.27

To evaluate X_LC(S) at 35 kHz, use Equation 28.

• Z_OUT(S) at 35 kHz, which is dominated by the output capacitor's ESR; estimated to be 400 mΩ
• Z_L(S) at 35 KHz is 7.25 Ω
• R_SW = 0.95 mΩ, including the R_LIM resistance
• R_SR = 100 mΩ

Using these numbers, X_LC(S) = 0.04 or –27.9 dB.

The feedback network has a gain to the error amplifier given using Equation 28.

Equation 28.

where

• for 3.3 V_OUT, R6 = 26.7 kΩ

Using the values in this application, K_fb = 11.4 dB.

The modulator has a gain of 10 that is flat to well beyond 35 kHz, so K_PWM = 20 dB.

To acheive 0-dB overall gain, the amplifier and feedback gain must be set to 7.9 dB (20 dB - 27.9 dB).

The amplifier gain, including the feedback gain, K_fb, can be approximated using Equation 29.

Equation 29.

where

• Z_FS is the parallel combination of C₇ in parallel with the sum of R₈ and the impedance of C₈
• A_VOL is the open-loop gain of the error amplifier at 35 kHz, which is 44.6 or 33 dB

Figure 38 shows the result of the compensation. The crossover frequency is 35 kHz, and the phase margin is 45°. The response of the system is dominated by the ESR of the output capacitor and is exploited to produce an essentially single-pole system with simple compensation.

Figure 38. Overall System Gain and Phase Response

Figure 38 also shows the phase boost that gives the system a crossover phase margin of 47°.

Table 2. Design Parameters

Table 3. Design Parameters