SLUS739F September   2006  – January 2016 TPS40200-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 MOSFET Gate Drive
      2. 7.3.2 Undervoltage Lockout Protection
      3. 7.3.3 Selecting the Operating Frequency
      4. 7.3.4 Synchronizing the Oscillator
      5. 7.3.5 Current-Limit Resistor Selection
      6. 7.3.6 Calculating the Soft-Start Time
      7. 7.3.7 Voltage Setting and Modulator Gain
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimum Input Voltage
      2. 7.4.2 Operation With SS Pin
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Regulator, 8-V to 12-V Input, 3.3-V or 5-V Output at 2.5 A
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 FET Selection Criteria
          2. 8.2.1.2.2 Rectifier Selection Criteria
          3. 8.2.1.2.3 Inductor Selection Criteria
          4. 8.2.1.2.4 Output Capacitance
          5. 8.2.1.2.5 Switching Frequency
          6. 8.2.1.2.6 Calculating the Overcurrent Threshold Level
          7. 8.2.1.2.7 Soft-Start Capacitor
          8. 8.2.1.2.8 Frequency Compensation
            1. 8.2.1.2.8.1 Step 1
            2. 8.2.1.2.8.2 Step 2
            3. 8.2.1.2.8.3 Step 3
            4. 8.2.1.2.8.4 Step 4
            5. 8.2.1.2.8.5 Step 5
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Application 2: 18-V to 50-V Input, 16-V Output at 1 A
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Application 3: Wide-Input-Voltage LED Constant-Current Driver
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Related Products
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage VDD, ISNS –0.3 52 V
RC, FB –0.3 5.5
SS –0.3 9
Output voltage COMP –0.3 9 V
GDRV VDD – 10 VDD
Lead temperature 1,6 mm (1/16 in) from case for 10 s 260 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±1000 V
Charged-device model (CDM), per AEC Q100-011 ±1500
Machine model (MM) ±100
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VDD Input voltage 4.5 52 V
TA Operating temperature –40 125 °C

6.4 Thermal Information

over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC(1) TPS40200-Q1 UNIT
D (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance 115.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 64.2 °C/W
RθJB Junction-to-board thermal resistance 56 °C/W
ψJT Junction-to-top characterization parameter 17.7 °C/W
ψJB Junction-to-board characterization parameter 55.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

–40°C < TA < 125°C, VDD = 12 V, fOSC = 100 kHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE REFERENCE
VFB Feedback voltage COMP = FB , 4.5 V < VDD < 52 V, –40°C < TA < 125°C 676 696 712 mV
GATE DRIVER
Isrc Gate driver pullup current 125 300 mA
Isnk Gate driver pulldown current 200 300 mA
VGATE Gate driver output voltage VGATE = (VDD – VGDRV), 12 V < VDD < 52 V 5.6 8 10 V
QUIESCENT CURRENT
Iqq Device quiescent current fOSC = 300 kHz, Driver not switching, 4.5 V < VDD < 52 V 1.5 3 mA
UNDERVOLTAGE LOCKOUT (UVLO)
VUVLO(on) Turn-on threshold –40°C < TA < 125°C 3.8 4.25 4.55 V
VUVLO(off) Turn-off threshold 4.05 V
VUVLO(HYST) Hysteresis 110 200 275 mV
SOFT START
RSS(chg) Internal soft-start pullup resistance 65 105 170 kΩ
RSS(dchg) Internal soft-start pulldown resistance 190 305 485 kΩ
VSSRST Soft-start reset threshold 100 150 200 mV
OVERCURRENT PROTECTION
VILIM Overcurrent threshold 4.5 V < VDD < 52 V, –40°C < TA < 125°C 50 100 140 mV
OCDF Overcurrent duty cycle(1) 2%
VILIM(rst) Overcurrent reset threshold 100 150 200 mV
OSCILLATOR
fOSC Oscillator frequency range(1) 35 500 kHz
Oscillator frequency RRC = 200 kΩ, CRC = 470 pF 85 100 118 kHz
RRC = 68.1 kΩ, CRC = 470 pF 210 300 345
Frequency line regulation 12 V < VDD < 52 V –9% 0%
4.5 V < VDD < 12 V –21% 0%
VRMP Ramp amplitude 4.5 V < VDD < 52 V VDD / 10 V
PULSE-WIDTH MODULATOR
tMIN Minimum controllable pulse width (2) VDD = 12 V 200 540 ns
VDD = 30 V 100 200
DMAX Maximum duty cycle Fosc = 100 kHz, CL = 470 pF 93% 95%
Fosc = 300 kHz, CL = 470 pF 90% 93%
KPWM Modulator and power-stage DC gain 8 10 12 V/V
ERROR AMPLIFIER
IIB Input bias current 100 250 nA
AOL Open loop gain(1) 60 80 dB
GBWP Unity gain bandwidth(1) 1.5 3 MHz
ICOMP(src) Output source current VFB = 0.6 V, COMP = 1 V 100 250 μA
ICOMP(snk) Output sink current VFB = 1.2 V, COMP = 1 V 1 2.5 mA
(1) Specified by design
(2) See Figure 21 for typical tMIN vs fOSC at various input voltages.

6.6 Typical Characteristics

TPS40200-Q1 icc_temp_lus659.gif
Figure 1. Quiescent Current vs Temperature
TPS40200-Q1 ssrt_temp.gif
Figure 3. Soft-Start Threshold vs Temperature
TPS40200-Q1 oscaf_temp_lus659.gif
Figure 5. Oscillator Frequency vs Temperature
TPS40200-Q1 oscf_vdd_lus659.gif
Figure 7. Oscillator Frequency vs VDD
TPS40200-Q1 gpwr_temp4512_lus659.gif
Figure 9. Power-Stage Gain vs Temperature
TPS40200-Q1 vramp_temp_lus659.gif
Figure 11. Modulator Ramp Amplitude vs Temperature
TPS40200-Q1 vramp_vdd_lus659.gif
Figure 13. Modulator Ramp Amplitude vs VDD
TPS40200-Q1 icompsrc_temp_lus659.gif
Figure 15. Comp Source Current vs Temperature
TPS40200-Q1 vgd_temp_lus659.gif
Figure 17. Gate Drive Voltage vs Temperature
TPS40200-Q1 vref_vdd2_lus659.gif
Figure 19. Reference Voltage vs Temperature
TPS40200-Q1 minpw_lus69.gif
Figure 21. Minimum Controllable Pulse Width vs Frequency
TPS40200-Q1 idd_vdd_lus659.gif
Figure 2. Quiescent Current vs VDD
TPS40200-Q1 uvlo_both_lus659.gif
Figure 4. UVLO Turn On and Turn Off vs Temperature
TPS40200-Q1 ilim_temp_12_lus659.gif
Figure 6. Current-Limit Threshold vs Temperature
TPS40200-Q1 gpwr_vdd_lus659.gif
Figure 8. Power-Stage Gain vs VDD
TPS40200-Q1 gpwr_temp2_lus659.gif
Figure 10. Power-Stage Gain vs Temperature
TPS40200-Q1 vramp_temp4_lus659.gif
Figure 12. Modulator Ramp Amplitude vs Temperature
TPS40200-Q1 iib_temp_lus659.gif
Figure 14. Feedback Amplifier Input Bias Current
vs Temperature
TPS40200-Q1 icmpsink_temp_lus659.gif
Figure 16. Comp Sink Current vs Temperature
TPS40200-Q1 vgd_vdd_lus659.gif
Figure 18. Gate Drive Voltage vs VIN
TPS40200-Q1 vref_temp_lus659.gif
Figure 20. Reference Voltage vs Temperature
TPS40200-Q1 dmax_vs_vvdd_lus659.gif
Figure 22. Maximum Duty Cycle vs Input Voltage