SLUSAF8E July 2011 – January 2016 TPS40322
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS40322 is a dual-output, synchronous buck controller, and it can also be configured as a two-phase controller.
This section explains the design process and component selection for a dual output synchronous buck converter using TPS40322 controller. The design goal parameters are listed in Table 3. The design procedure provides calculations for channel 1 only. User can apply similar calculation for channel 2.
Figure 23 shows the dual output converter schematic for this design example.
The design goal parameters are listed in Table 3.
PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT CHARACTERISTICS | ||||||
V_{IN} | Input voltage | 8 | 12 | 15 | V | |
V_{IN(ripple)} | Input ripple | I_{OUT1} = I_{OUT2} = 10 A | 0.25 | V | ||
OUTPUT 1 CHARACTERISTICS | ||||||
V_{OUT1} | Output voltage | I_{OUT1(min)} ≤ I_{OUT1} ≤ I_{OUT1(max)} | 1.2 | V | ||
Line regulation | V_{IN(min)} ≤ V_{IN} ≤ V_{IN(max)} | 0.5% | ||||
Load regulation | I_{OUT1(min)} ≤ I_{OUT1} ≤ I_{OUT1(max)} | 0.5% | ||||
V_{RIPPLE1} | Output ripple | I_{OUT1 }= I_{OUT1(max)} | 24 | mV | ||
V_{OVER1} | Output overshoot | ΔI_{OUT1} = 5 A | 40 | mV | ||
V_{UNDER1} | Output undershoot | ΔI_{OUT1} = 5A | 40 | mV | ||
I_{OUT1} | Output current | V_{IN(min)} ≤ V_{IN} ≤ V_{IN(max)} | 0 | 10 | A | |
I_{SCP1} | Short circuit current trip point | 15 | A | |||
OUTPUT 2 CHARACTERISTICS | ||||||
V_{OUT2} | Output voltage | I_{OUT2(min)} ≤ I_{OUT2} ≤ I_{OUT2(max)} | 1.8 | V | ||
Line regulation | V_{IN(min)} ≤ V_{IN} ≤ V_{IN(max)} | 0.5% | ||||
Load regulation | I_{OUT2(min)} ≤ I_{OUT2} ≤ I_{OUT2(max)} | 0.5% | ||||
V_{RIPPLE2} | Output ripple | I_{OUT2 }= I_{OUT2(max)} | 36 | mV | ||
V_{OVER2} | Output overshoot | ΔI_{OUT2} = 5 A | 40 | mV | ||
V_{UNDER2} | Output undershoot | ΔI_{OUT2} = 5 A | 40 | mV | ||
I_{OUT2} | Output current | V_{IN(min)} ≤ V_{IN} ≤ V_{IN(max)} | 0 | 10 | A | |
I_{SCP2} | Short circuit current trip point | 15 | A | |||
GENERAL CHARACTERSTICS | ||||||
t_{SS} | Soft-start time | V_{IN} = 12 V | 2 | ms | ||
η | Efficiency | V_{IN} = 12 V, I_{OUT1}= I_{OUT2} = 10 A | 88% | |||
f_{SW} | Switching frequency | 500 | kHz |
Inductor Selection (L1) through General Device Components show equations and calculations regarding V_{OUT1}. V_{OUT2} values can be calculated using similar equations. See Table 4 for the list of materials.
REFERENCE DESIGNATOR |
QTY | DESCRIPTION | PART NUMBER | MFR |
---|---|---|---|---|
C1 | 1 | Capacitor, Aluminum, 100 µF, 35 V, ±20%, 0.328 x 0.328 inch | EEV-FK1V101GP | Panasonic - ECG |
C2, C7, C20, C26, C39 | 5 | Capacitor, Ceramic, 0.1 µF, 50 V, X7R, ±10%, 0603 | Std | Std |
C3, C35 | 2 | Capacitor, Ceramic, 0.1 µF, 25 V, X5R, ±10%, 0402 | Std | Std |
C4, C36 | 2 | Capacitor, Ceramic, 1.0 µF, 25 V, X7R, ±10%, 0603 | Std | Std |
C5, C6, C37, C38 | 4 | Capacitor, Ceramic, 10 µF, 25 V, X5R, ±10%, 0805 | Std | Std |
C8, C25 | 2 | Capacitor, Ceramic, 33 nF, 16 V, X7R, ±10%, 0603 | Std | Std |
C9, C19, C22, C34 | 4 | Capacitor, Ceramic, 470 pF, 25 V, C0G, NP0, ±5%, 0603 | Std | Std |
C10, C27 | 2 | Capacitor, Ceramic, 1.0 µF, 6.3 V, X5R, ±10%, 0402 | Std | Std |
C11, C12, C18, C28, C29 | 5 | Capacitor, Ceramic, 3.3 µF, 10 V, X5R, ±10%, 0603 | C1608X5R1A335K | TDK Corporation |
C13, C14, C30, C31 | 4 | Capacitor, Ceramic, 10 µF, 6.3 V, X7R, ±10%, 0805 | Std | Std |
C15, C16, C32, C33 | 4 | Capacitor, Polymer Aluminum, 220 µF, 4 V, ±20%, 5 mΩ ESR | EEF-SE0G221ER | Panasonic - ECG |
C17, C23 | 2 | Capacitor, Ceramic, 220 pF, 50 V, C0G, NP0, ±5%, 0603 | Std | Std |
C21, C24 | 2 | Capacitor, Ceramic, 10 pF, 50 V, C0G, NP0, ±5%, 0603 | Std | Std |
C40 | 1 | Capacitor, Ceramic, 1.0 nF, 25 V, C0G, NP0, ±5%, 0603 | Std | Std |
L1, L2 | 2 | Inductor, Power Choke, 1.1 µH, ±20%, 3.15 mΩ, 7.0 mm x 6.9 mm | 744314110 | Wurth Elektronik |
Q1, Q2 | 2 | MOSFET, Synchronous Buck NexFET Power Block, QFN-8 POWER | CSD86330Q3D | Texas Instruments |
R1 | 1 | Resistor, Chip, 68.1 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R2, R21 | 2 | Resistor, Chip, 86.6 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R3 | 1 | Resistor, Chip, 12.7 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R4, R5, R22 | 3 | Resistor, Chip, 1.00 Ω, 1/10 W, ±1%, 0603 | Std | Std |
R6 | 1 | Resistor, Chip, 40.2 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R7, R24 | 2 | Resistor, Chip, 49.9 Ω, 1/10 W, ±1%, 0603 | Std | Std |
R8, R17 | 2 | Resistor, Chip, 5.11 Ω, 1/8 W, ±1%, 0805 | Std | Std |
R9, R16 | 2 | Resistor, Chip, 0 Ω, 1/10 W, ±1%, 0603 | Std | Std |
R10, R14, R19, R27 | 4 | Resistor, Chip, 20.0 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R11, R18 | 2 | Resistor, Chip, 82.5 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R12, R23 | 2 | Resistor, Chip, 1.62 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R13 | 1 | Resistor, Chip, 3.09 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R15 | 1 | Resistor, Chip, 29.4 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R20, R30 | 2 | Resistor, Chip, 5.11 Ω, 1/10 W, ±1%, 0603 | Std | Std |
R25 | 1 | Resistor, Chip, 10.0 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R26 | 1 | Resistor, Chip, 3.24 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R28, R29 | 2 | Resistor, Chip, 100 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
U1 | 1 | TPS40322 Dual Synchronous Buck Controller, QFN-32 | TPS40322RHB | Texas Instruments |
To maintain acceptable efficiency and meet minimum on-time requirements, a 500-kHz switching frequency is selected.
Synchronous BUCK power inductors are typically sized for approximately 20%–40% peak-to-peak ripple current (I_{RIPPLE}). Given a target ripple current of 30%, the required inductor size, at maximum rated output current, can be calculated using Equation 8.
Selecting a standard, readily available inductor, with a rated inductance is 0.88 µH at 10 A, I_{RIPPLE1} = 2.5 A.
The RMS current through the inductor is approximated by the equation:
The selection of the output capacitor is typically driven by the output transient response requirement. Equation 10 and Equation 11 over-estimate the voltage deviation to account for delays in the loop bandwidth and can be used to determine the required output capacitance:
When V_{IN(min) }> 2 x V_{OUT1}, use the overshoot equation, V_{OVER1}, to calculate minimum output capacitance. When V_{IN(min) } < 2 x V_{OUT1} use Equation 11, V_{UNDER1}, to calculate minimum output capacitance. In this design example, V_{IN(min)} is much larger than 2 x V_{OUT1} so Equation 12 is used to determine the required minimum output capacitance.
With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is approximated by Equation 13.
Two 220-µF, 4-V, aluminum electrolytic capacitors were chosen for load response requirements. Additionally two 0805 10-µF, X7R, along with two 0603, 3.3-µF X5R, and one 1-µF, X5R ceramic capacitors are selected for low ESR and high frequency decoupling.
With the output capacitance known, it is possible to calculate the charge current during start-up and determine the minimum saturation current rating for the inductor. The start-up charging current is approximated using Equation 14.
PARAMETER | VALUE | UNIT | |
---|---|---|---|
L1 | Inductance | 0.88 | µH |
IL1_RMS | RMS current (thermal rating) | 10.026 | A |
IL1_PEAK | Peak current (saturation rating) | 11.53 | A |
A 744314110 from Wurth Electronics with 1.1-µH zero current inductance is selected. Inductance for this part is 0.88-µH at 10-A bias. This 15-A, 3.15-mΩ inductor exceeds the minimum inductor ratings in a 7-mm x 7-mm package.
The input voltage ripple is divided between the capacitance and ESR of the input capacitor. For this design V_{RIPPLE(cap)} = 200 mV and V_{RIPPLE(esr)} = 50 mV. The minimum capacitance and maximum ESR are estimated using Equation 16.
The RMS current in the input capacitors is estimated using Equation 18.
To achieve these goals, two 0805, 10-µF capacitors, one 0605, 1.0-µF capacitor and one 0402, 0.1-µF X5R ceramic capacitor are combined at the input.
Texas Instruments CSD86330, 20-A power block device was chosen. This device incorporates the high-side and low-side MOSFETs in a single 3 mm x 3 mm package. The high-side MOSFET has an on-resistance (R_{DS(on)}) of 8.8 mΩ, while the low-side on-resistance (R_{DS(on)}) is 4.6 mΩ, both at 4.5 V gate voltage. A 5.11-Ω gate resistor is used on the HDRV pin on each device for added noise immunity.
The output current is sensed across the DCR of the L1 output inductor. An RC combination having a time constant equal to that of the L1 inductance and the DCR is used to extract the current information as a voltage. A standard capacitor value of 0.1-µF is used. The resistor, R13, can be calculated using Equation 20.
A standard 3.09-kΩ resistor was selected.
This design limits the maximum voltage drop across the current sense inputs, V_{CS(max)}, to 50 mV. If the voltage drop across the DCR of the inductor is greater than V_{CS(max)}, after allowing for 20% overshoot spikes and a 20% variation in the DCR value, then a resistor is added to divide the voltage down to 50 mV. The divider resistor, R15, is calculated by Equation 21.
where
The maximum DCR voltage drop is given by Equation 22.
The current limit resistor is calculated using the minimum ILIM programming current, I_{ILIM(min)}, the maximum current sense amplifier gain, A_{CS}, and assuming a current sense amplifier minimum input offset voltage, V_{OS(min)} equal to –3 mV.
The TPS40322 controller uses a full operational amplifier with an internally fixed 0.600-V reference. Tha value for R10 is selected between 10-kΩ and 50-kΩ for a balance of feedback current and noise immunity. With the R10 resistor set to 20-kΩ, the output voltage is programmed with a resistor divider given by Equation 24.
Using the TPS40k Loop Stability Tool for an 85-kHz bandwidth and 50° of phase margin with an R10 value of 20.0 kΩ, and measuring the theoretical results in the laboratory and modifying accordingly for system optimization yields the following values:
To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to < 100 mV.
The SYNC pin must be left open for independent dual outputs.
The desired switching frequency is programmed by the current through R_{RT} to GND. the value of R_{RT} is calculated using Equation 26.
In dual output configuration the DIFFO pin is not used and must remain open (unconnected).
The soft-start capacitor provides smooth ramp of the error amplifier reference voltage for controlled start-up. The soft-start capacitor is selected using Equation 27.
PG1 and PG2 can each be pulled up to BP6 through a 100-kΩ resistor, or remain not-connected. For sequencing the start-up of output 1 before output 2, connect PG1 to EN2/SS2; for sequencing the start-up of output 2 before output 1, connect PG2 to EN1/SS1.
The PHSET pin can be connected to ground or connected to the BP6 pin.
The UVLO hysteresis level is programmed by R1 with Equation 28 and Equation 29.
As shown in the Pin Configuration and Functions section, use a 0.1-µF, 50-V, X7R capacitor for VDD bypass.
Select a 3.3-µF (or greater) low ESR capacitor for BP6. For this design use a 3.3-µF, X5R ceramic capacitor.
Figure 28 shows the switching waveform, V_{IN} = 12 V, I_{OUT1} = I_{OUT2} = 10 A, Ch.1 = HDRV1, Ch.2 = LDRV1, Ch.3 = VOUT1 ripple. The high-frequency noise is caused by parasitic inductive and capacitive elements interacting with the high energy, rapidly switching power elements resulting in ringing at the transition points. Capacitive filtering at the load input will successfully attenuate these noise spikes.
Figure 29 shows the schematic, waveforms, and components for a two-phase, single output synchronous buck converter using the TPS40322 controller. The design goal parameters are given in Table 7.
Table 6 summaries the channel 2 related pin connection in two-phase mode.
PIN NAME | CONNECTION | |||
---|---|---|---|---|
COMP2 | Connect to COMP1 | |||
EN2/SS2/GSNS | Use as GSNS pin, connect to the output ground | |||
FB2 | Connect to BP6 | |||
ILIM2/VSNS | Use as VSNS pin, connect to output | |||
PG2 | Floating or connect to ground |
The design goal parameters are listed in Table 7.
PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
V_{IN} | Input voltage | 4.5 | 15 | V | ||
V_{OUT} | Output voltage | I_{OUT(min)} ≤ I_{OUT} ≤ I_{OUT(max)} | 1.2 | V | ||
Line regulation | V_{IN(min)} ≤ V_{IN} ≤ V_{IN(max)} | 0.5% | ||||
Load regulation | I_{OUT(min)} ≤ I_{OUT} ≤ I_{OUT(max)} | 0.5% | ||||
V_{RIPPLE} | Output ripple | I_{OUT1 }= I_{OUT1(max)} | 12 | mV | ||
V_{OVER} | Output overshoot | ΔI_{OUT1} = 5 A | 40 | mV | ||
V_{UNDER} | Output undershoot | ΔI_{OUT1} = 5A | 40 | mV | ||
I_{OUT} | Output current | V_{IN(min)} ≤ V_{IN} ≤ V_{IN(max)} | 0 | 30 | A | |
t_{SS} | Soft-start time | V_{IN} = 12 V | 2 | ms | ||
η | Efficiency | V_{IN} = 12 V, I_{OUT1} = I_{OUT2} = 10 A | 88% | |||
f_{SW} | Switching frequency | 500 | kHz |
Inductor Selection (L1) through General Device Components show equations and calculations regarding V_{OUT1}. V_{OUT2} values can be calculated using similar equations. See Table 8 for the list of materials.
REFERENCE DESIGNATOR |
QTY | DESCRIPTION | PART NUMBER | MFR |
---|---|---|---|---|
C1, C2, C3, C31, C32, C33 | 6 | Capacitor, Ceramic, 22 µF, 25 V, X5R, ±20%, 1210 | Std | Std |
C4, C18, C28, C30 | 4 | Capacitor, Ceramic, 1 µF, 50 V, X7R, ±10%, 0603 | Std | Std |
C5, C6, C7, C22, C29 | 5 | Capacitor, Ceramic, 0.1 µF, 50 V, X7R, ±10%, 0603 | Std | Std |
C8, C21 | 2 | Capacitor, Ceramic, 6.8 nF, 50 V, X7R, ±10%, 0805 | Std | Std |
C9 | 1 | Capacitor, Ceramic, 2.2 nF, 16 V, X7R, ±10%, 0603 | Std | Std |
C10, C11, C12, C13, C23, C24, C25, C26 | 8 | Capacitor, Polymer Aluminum, 220 µF, 4 V, ±20%, 5mΩ ESR | EEFSE0G221R | Panasonic - ECG |
C14, C27 | 2 | Capacitor, Ceramic, 22 µF, 6.3 V, X5R, ±10%, 0805 | Std | Std |
C15 | 1 | Capacitor, Ceramic, 8.2 nF, 16 V, X7R, ±10%, 0603 | Std | Std |
C16 | 1 | Capacitor, Ceramic, 330 pF, 16 V, X7R, ±10%, 0603 | Std | Std |
C17 | 1 | Capacitor, Ceramic, 22 nF, 50 V, X7R, ±10%, 0603 | Std | Std |
C19, C20 | 2 | Capacitor, Ceramic, 4.7 µF, 16 V, X7R, ±10%, 0805 | Std | Std |
C38, C39 | 2 | Capacitor, Aluminum, 100 µF, 25 V, ±20%, F8 | ECE-V1EA101XP | Panasonic - ECG |
L1, L2 | 2 | Inductor, SMT, 0.47 µH, ±20%, 1.2 mΩ, 0.512" x 0.571" | IHLP5050FDERR47M01 | Vishay/Dale |
Q1, Q4 | 2 | MOSFET, N-channel, 30 V, 30 A, 8 mΩ, 5-LFPAK | RJK0305 | Renesas Electronics |
Q2, Q3 | 2 | MOSFET, N-channel, 30 V, 60 A, 2.1 mΩ, 5-LFPAK | RJK0328 | Renesas Electronics |
R1 | 1 | Resistor, Chip, 42 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R2 | 1 | Resistor, Chip, 100 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R3, R19 | 2 | Resistor, Chip, 4.7 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R4 | 1 | Resistor, Chip, 38.5 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R5 | 1 | Resistor, Chip, 49.9 Ω, 1/10 W, ±1%, 0603 | Std | Std |
R6, R8, R16 | 3 | Resistor, Chip, 10 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R7, R27, R28, R29, R30 | 5 | Resistor, Chip, 0 Ω, 1/10 W, ±1%, 0603 | Std | Std |
R9 | 1 | Resistor, Chip, 511 Ω, 1/10 W, ±1% | Std | Std |
R10, R17 | 1 | Resistor, Chip, 1.00 Ω, 1/8 W, ±1%, 0805 | Std | Std |
R11, R18 | 2 | Resistor, Chip, 5.11 Ω, 1/10 W, ±1% 0603 | 603 | Std |
R12, R13 | 2 | Resistor, Chip, 51 Ω, 1/10 W, ±1%, 0603 | Std | Std |
R14 | 1 | Resistor, Chip, 3.32 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R15 | 1 | Resistor, Chip, 40 kΩ, 1/10 W, ±1%, 0603 | Std | Std |
R26, R31 | 2 | Resistor, Chip, 2 Ω, 1/10 W, ±1%, 0603 | Std | Std |
R20, R21, R22, R23, R24, R25, | 0 | not used | Std | Std |
U1 | 1 | Dual synchronous buck controller, QFN-32 | TPS40322RHB | Texas Instruments |