SLUSAF8E July   2011  – January 2016 TPS40322


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Voltage Reference
      2. 7.3.2  Output Voltage Setting
      3. 7.3.3  Input Voltage Feedforward
      4. 7.3.4  Current Sensing
      5. 7.3.5  Overcurrent Protection
      6. 7.3.6  Two-Phase Mode, Remote Sense Amplifier, and Current Sharing Loop
      7. 7.3.7  Start-Up and Shutdown
        1. Start-Up Sequence
        2. Prebiased Output Start-Up
        3. Shutdown
      8. 7.3.8  Switching Frequency and Master or Slave Synchronization
      9. 7.3.9  Overvoltage and Undervoltage Fault Protection
      10. 7.3.10 Input Undervoltage Lockout (UVLO)
      11. 7.3.11 Power Good
      12. 7.3.12 Thermal Shutdown
      13. 7.3.13 Connection of Unused Pins
    4. 7.4 Device Functional Modes
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Dual-Output Configuration from 12-V Nominal to 1.2-V and 1.8-V DC-to-DC Converter Using the TPS40322
        1. Design Requirements
        2. Detailed Design Procedure
          1.  Selecting a Switching Frequency
          2.  Inductor Selection (L1)
          3.  Output Capacitor Selection (C10 through C16)
          4.  Peak Current Rating of Inductor
          5.  Input Capacitor Selection (C3 through C6)
          6.  MOSFET Selection (Q1)
          7.  ILIM Resistor (R2)
          8.  Feedback Divider (R10, R14)
          9.  Compensation: (R11, R12, C17, C19, C21)
          10. Boot-Strap Capacitor (C7)
          11. General Device Components
            1. Synchronization (SYNC Pin)
            2. RT Resistor (R6)
            3. Differential Amplifier Out (DIFFO Pin)
            4. EN/SS Timing Capacitors (C8)
            5. Power Good (PG1, PG2 Pins)
            6. Phase Set (PHSET Pin)
            7. UVLO Programming Resistors (R1 and R3)
            8. VDD Bypass Capacitor (C2)
            9. VBP6 Bypass Capacitor (C18)
        3. Application Curves
      2. 8.2.2 Two-Phase, Single Output Configuration from 12-V nominal to 1.2-V DC-to-DC Converter Using the TPS40322
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Stage
      2. 10.1.2 Device Peripheral
      3. 10.1.3 Thermal Pad Layout
    2. 10.2 Layout Example
    3. 10.3 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

10.1.1 Power Stage

A synchronous BUCK power stage has two primary current loops. The input current loop carries high AC discontinuous current while the output current loop carries high DC continuous current. The input current loop includes the input capacitors, the main switching MOSFET, the inductor, the output capacitors and the ground path back to the input capacitors. To maintain the loop as small as possible, it is generally good practice to place some ceramic capacitance directly between the drain of the main switching MOSFET and the source of the synchronous rectifier (SR) through a power ground plane directly under the MOSFETs. The output current loop includes the SR MOSFET, the inductor, the output capacitors, and the ground return between the output capacitors and the source of the SR MOSFET. As with the input current loop, the ground return between the output capacitor ground and the source of the SR MOSFET must be routed under the inductor and SR MOSFET to minimize the power loop area. The SW node area must be as small as possible to reduce the parasitic capacitance and minimize the radiated emissions. The gate drive loop impedance (HDRV-gate-source-SW and LDRV-gate-source- GND) must be kept to as low as possible. The HDRV and LDRV connections must widen to 20 mils as soon as possible out from the device pin.

10.1.2 Device Peripheral

The TPS40322 provides separate signal ground (AGND) and power ground (PGND1 and PGND2) pins. It is required to properly separate the circuit grounds. The return path for the pins associated with the power stage must be through PGND. The other pins (especially for those sensitive pins such as FB1, FB2, RT, ILIM1, and ILIM2) must be through the low noise AGND. The AGND and PGND planes are suggested to be connected at the output capacitor with single 20-mil trace. A minimum 0.1-µF ceramic capacitor must be placed as close to the VDD pin and AGND as possible with at least 15-mil wide trace from the bypass capacitor to the AGND. A minimum value of 3.3-µF ceramic capacitor must be connected from BP6 to PGND, placed as close to the BP6 pin as possible. When DCR sensing method is applied, the sensing resistor must be placed close to the SW node and connected to the inductor with a kelvin connection. The sensing traces from the power stage to the chip must be away from the switching components. The sensing capacitor must be placed very close to the CS+ and CS- pins for each output. The frequency setting resistor must be placed as close to RT pin and AGND as possible. In two-phase mode, the ILIM2/VSNS and EN2/SS2/GSNS pins must be directly connected to the point of load where the voltage regulation is required. A parallel pair of 10-mil traces connects the regulated voltage back to the chip. They must be away from the switching components.

10.1.3 Thermal Pad Layout

The Thermal pad package provides low thermal impedance for heat removal from the device. The Thermal pad derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend on the size of the Thermal pad package.

Thermal vias connect this area to internal or external copper planes and must have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz. copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material must be used to cap the vias with a diameter equal to the via diameter plus 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package.

10.2 Layout Example

TPS40322 layout_example_slusaf8.gif Figure 33. Layout Example

10.3 Mounting and Thermal Profile Recommendation

Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the reflow process can affect electrical performance. Figure 34 shows the recommended reflow oven thermal profile. Proper post-assembly cleaning is also critical to device performance. See SLUA271 for more information.

TPS40322 mech_thermal_profile.gif Figure 34. Recommended Reflow Oven Thermal Profile

Table 9. Recommended Thermal Profile Parameters

rRAMP(up) Average ramp-up rate, TS(max) to TP 3 °C/s
rRAMP(down) Average ramp-down rate, TP to TS(max) 6 °C/s
TS Pre-Heat temperature 150 200 °C
tS Pre-heat time, TS(min) to TS(max) 60 180 s
TL Liquidus temperature 217 °C
TP Peak temperature 260 °C
tL Time maintained above liquidus temperature, TL 60 150 s
tP Time maintained within 5°C of peak temperature, TP 20 40 s
t25P Total time from 25°C to peak temperature, TP 480 s