SLUSEE5D January   2022  – April 2024 TPS4811-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Charge Pump and Gate Driver output (VS, PU, PD, BST, SRC)
      2. 8.3.2  Capacitive Load Driving
        1. 8.3.2.1 FET Gate Slew Rate Control
        2. 8.3.2.2 Using Precharge FET - (with TPS48111-Q1 Only)
      3. 8.3.3  Short-Circuit Protection
        1. 8.3.3.1 Overcurrent Protection With Auto-Retry
        2. 8.3.3.2 Overcurrent Protection With Latch-Off
      4. 8.3.4  Short-Circuit Protection
      5. 8.3.5  Analog Current Monitor Output (IMON)
      6. 8.3.6  Overvoltage (OV) and Undervoltage Protection (UVLO)
      7. 8.3.7  Device Functional Mode (Shutdown Mode)
      8. 8.3.8  Remote Temperature sensing and Protection (DIODE)
      9. 8.3.9  Output Reverse Polarity Protection
      10. 8.3.10 TPS4811x-Q1 as a Simple Gate Driver
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving HVAC PTC Heater Load on KL40 Line in Power Distribution Unit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application: Driving B2B FETs With Pre-charging the Output Capacitance
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

TJ = –40℃ to +125℃; typical values at TJ = 25°C, V(VS) = V(CS+) = V(CS–) = 48 V, V(BST – SRC) = 12 V, V(SRC) = 0 V, VSNS = Voltage across RSNS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPU(INP_H) INP Turn ON propogation Delay INP ↑ to PU  ↑, CL = 47 nF 1 2 µs
tPD(INP_L) INP Turn OFF propogation Delay INP ↓ to PD  ↓, CL = 47 nF 1 µs
tG(INP_G_H) INP_G Turn ON propogation Delay INP_G ↑ to G  ↑, CL = 1 nF 21 µs
tG(INP_G_L) INP_G Turn OFF propogation Delay INP_G ↓ to G  ↓, CL = 1 nF 0.55 0.8 µs
tPD(EN_OFF) EN Turn OFF Propogation Delay  EN ↓ to PD  ↓, CL = 47 nF 3.2 5 µs
tPD(UVLO_OFF) UVLO Turn OFF Propogation Delay  UVLO ↓ to PD  ↓, CL = 47 nF 3.5 6 µs
tPD(VS_OFF) PD Turn OFF delay during input supply (VS) interruption VS ↓ V(VS_PORF) to PD  ↓, CL = 47 nF, INP = EN/UVLO = 2 V 54 µs
tPU(VS_ON) PU Turn ON delay during input supply (VS) recovery VS ↑ V(VS_PORR) to PU  ↑, CL = 47 nF, INP = EN/UVLO = 2 V, V(BST–SRC) > V(BST_UVLOR) 328 465 µs
tPD(OV_OFF) OV Turn Off progopation Delay OV ↑ to PD  ↓, CL = 47 nF 2.6 4 µs
tSC Short-circuit protection propogation Delay (VCS+ – VCS–) ↑ V(SNS_SCP) to PD ↓, CL = 47 nF, TPS48111-Q1 Only 1.16 1.6 µs
Short-circuit protection propogation Delay (VCS+ – VCS–) ↑ V(SNS_SCP)  to PD  ↓, CL = 47 nF, TPS48110–Q1 Only 4 5 µs
tOC Over current protection delay  (VCS+ – VCS–) ↑ V(SNS_WRN) to PD ↓, CL = 47 nF, CTMR = 0 nF 25 30 µs
Over current protection delay  (VCS+ – VCS–) ↑ V(SNS_WRN) to PD ↓, CL = 47 nF, CTMR = 22 nF 370 µs
t(FLT_I_ASSERT) FLT_I assertion delay CTMR = 22 nF 340 µs
t(FLT_I_DEASSERT) FLT_I de-assertion delay 260 µs
t(FLT_T)AR TSD Auto-retry  TPS48110-Q1 Only 512 msec