SLVSBF0C JULY   2012  – April 2019 TPS53015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Drivers
      2. 7.3.2 5-Volt Regulator
      3. 7.3.3 Soft-Start and Pre-biased Soft-Start Time
      4. 7.3.4 Overcurrent Protection
      5. 7.3.5 Overvoltage and Undervoltage Protection
      6. 7.3.6 UVLO Protection
      7. 7.3.7 Thermal Shutdown
      8. 7.3.8 Power Good
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Operation
      2. 7.4.2 Auto-skip Eco-Mode Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Determine the Inductance Value
        2. 8.2.2.2 Output Capacitor
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Bootstrap Capacitor
        5. 8.2.2.5 VREG5 Capacitor
        6. 8.2.2.6 Choose Output Voltage Resistors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

Considerations these design guidelines before beginning the application layout process.

  • Design an input switching current loop as small as possible.
  • Place the input capacitor close to the top switching FET.
  • Design the output switching current loop as small as possible.
  • The SW node must be physically small and as short as possible as to minimize parasitic capacitance and inductance and to minimize radiated emissions.
  • Bring Kelvin connections from the output to the feedback pin (VFB) of the device.
  • Place analog and non-switching components far away from switching components.
  • Make a single point connection from the signal ground to power ground.
  • Do not allow switching current to flow under the device.