SLUSC63A November   2015  –  December 2015 TPS53317A


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation
      2. 7.3.2 PWM Frequency and Adaptive On-Time Control
      3. 7.3.3 Light-Load Power Saving Features
      4. 7.3.4 Power Sequences
        1. Non-Tracking Startup
        2. Tracking Startup
      5. 7.3.5 Protection Features
        1. 5-V Undervoltage Protection (UVLO)
        2. Power Good Signals
        3. Output Overvoltage Protection (OVP)
        4. Output Undervoltage Protection (UVP)
        5. Overcurrent Protection
          1. Overcurrent Limit
          2. Negative OCL
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Non-Droop Configuration
      2. 7.4.2 Droop Configuration
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 DDR4 SDRAM Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. Step 1. Determine Configuration
          2. Step 2. Select Inductor
          3. Step 3. Determine Output Capacitance
          4. Step 4. Input Capacitance
          5. Step 5. Compensation Network
          6. Peripheral Component Selection
        3. Application Curves
      2. 8.2.2 DDR3 SDRAM Application
        1. Design Requirements
      3. 8.2.3 Non-Tracking Point-of-Load (POL) Application
        1. Design Requirements
        2. Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS53317A device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with both sink and source capability. The device employs D-CAP+ mode operation that provides ease-of-use, low external component count and fast transient response.

8.2 Typical Applications

8.2.1 DDR4 SDRAM Application

This DDR4 application requires a tight load tolerance, fast transient response, and sinking current capability, the design uses a non-droop PWM configuration.

TPS53317A de_tracking_slusc63.gif Figure 30. DDR4 SDRAM Application Design Requirements

  • Input voltage : VIN = 1.2 V
  • Output voltage: VOUT = 0.6 V
  • Maximum load step size of 3 A @ slew rate 7 A/µs (–1.5 A to 1.5 A)
  • DC +AC + Ripple voltage regulation limit at sense point: ±42 mV (0.642 V overshoot, 0.558 V undershoot)
  • Maximum load: IMAX = 2.5 A Detailed Design Procedure Step 1. Determine Configuration

Because this DDR4 application requires a tight load tolerance, fast transient response, and sinking current capability, the design uses a non-droop PWM configuration. Choose 600-kHz switching frequency due to the duty cycle and minimim off-time of the device, and set an overcurrent (OC) valley limit of 5.4 A due to the maximum load requirement of 2.5 A. Referring to Table 1 select an RMODE value of 68 kΩ. Step 2. Select Inductor

Smaller inductor values have better transient performance but higher ripple and lower efficiency. High values have the opposite characteristics. It is common practice to limit the ripple current to 30% to 50% of the maximum current. Choose 50% to allow use of a smaller inductor for faster transient performance.

Equation 7. TPS53317A q_deltap2p_slusak4.gif
Equation 8. TPS53317A q_de_l_slusak4.gif


  • D = duty cycle

Because this device operates in DCAP+ mode, the frequency and duty cycle vary based on the input voltage, the output voltage and load. With a 2.5-A load, a 1.2-V input voltage and 0.60 V output voltage, fSW is experimentally measured at approximately 800 kHz and duty cycle of 0.55. Therefore L is calculated as shown in Equation 10.

Equation 9. TPS53317A q_de_l2_slusak4.gif

Choose the closest standard value, 0.25 µH. Step 3. Determine Output Capacitance

Use Equation 10 to calculate the output capacitance for a desired maximum overshoot.

Equation 10. TPS53317A q_coutminos_slusak4.gif


  • COUT(min),OS is the minimum output capacitance for a desired overshoot
  • ΔIOUT is the maximum output current change in the application
  • VOUT = desired output voltage
  • VOS is the desired output voltage change due to overshoot

Choose a value of 30 mV to account for normal output voltage ripple.

Equation 11. TPS53317A q_de_coutminos2_slusak4.gif

Use Equation 12 to calculate the necessary output capacitance for a desired maximum undershoot.

Equation 12. TPS53317A q_de_coutminus_slusak4.gif


  • COUT(min),US is the minimum output capacitance for a desired undershoot
  • VUS is the desired output voltage change due to overshoot
  • tSW is the period of switch node
  • tMIN(off) is the minimum off-time (270 ns)

Again, choose 30 mV to account for normal output voltage ripple.

Equation 13. TPS53317A q_de_coutminus2_slusak4.gif

The undershoot requirements determine, so there must be a minimum of 157.6 µF. Because this is a DDR application where size is also a consideration, this design uses only ceramic capacitors. To account for voltage de-rating of capacitors and provide additional margin, this design includes eleven 22-µF output capacitors. Step 4. Input Capacitance

This design requires sufficient input capacitance to filter the input current from the host source. Use Equation 14 to calculate the necessary input capacitance.

Equation 14. TPS53317A q_de_cinmin_slusak4.gif


  • ΔVIN(P-P) is the desired input voltage ripple (typically 1% of the input voltage)
Equation 15. TPS53317A q_de_cinmin2_slusak4.gif

As with the output capacitance selection, this design accounts for voltage de-rating of capacitors and provides additional margin, using four 22-µF input capacitors. Step 5. Compensation Network

In order to achieve stable operation, the crossover frequency should be less than 1/5 of the switching frequency.

Equation 16. TPS53317A q_de_fco_slusak4.gif


  • RS = 53 mΩ

Account for capacitor de-rating here and set the value of COUT to 160 µF, so that Equation 17 is true.

Equation 17. TPS53317A q_de_rc_slusak4.gif

Choose an RC value of 3.9 kΩ. Determine CC by choosing the value of the zero created by RC and CC. Using the relationship described in Equation 18.

Equation 18. TPS53317A q_de_fz_slusak4.gif

Equation 18 yields a CC value of 2.55 nF. Choose the closest common capacitor value of 2.2 nF. To determine a value for CP, first consider the relationship described in Equation 19.

Equation 19. TPS53317A q_de_fp_slusak4.gif


  • CC >> CP

Because CC >> CP , set the pole to be two times the switching frequency as described in Equation 20.

Equation 20. TPS53317A q_de_cp_slusak4.gif

To boost the gain margin, set CP to 33 pF.

TPS53317A comp_ntwrk_slusc63.gif Figure 31. Compensation Network Circuit Peripheral Component Selection

As described in Table 1, connect a 0.22-µF capacitor from the VREF pin to GND and connect a 0.1-µF bootstrap capacitor from the SW pin to the BST pin. Because the PGOOD pin is open drain, connect a pullup resistor between it and the 5-V rail. Application Curves

TPS53317A C018_SLUSAK4.png
Figure 32. Efficiency
TPS53317A C014_SLUSAK4.png Figure 34. Bode Plot, No Load
TPS53317A D100_SLUSC63.gif
VIN = 1.2 fSW = 600 kHz
Figure 36. Switching Frequency vs. Load
TPS53317A de_load_transient_slusak4.gif Figure 33. Load Transient
TPS53317A C015_SLUSAK4.png Figure 35. Bode Plot, Full Load
TPS53317A C019_SLUSAK4.png
Figure 37. Load Regulation

8.2.2 DDR3 SDRAM Application

TPS53317A de_tracking_slusc63.gif Figure 38. Typical Application Schematic, DDR3 Design Requirements

  • VIN = 1.5 V
  • VOUT = 0.75 V

8.2.3 Non-Tracking Point-of-Load (POL) Application

TPS53317A de_nontracking_slusc63.gif Figure 39. Typical Application Schematic, Non-Tracking Point-of-Load (POL) Design Requirements

  • VIN = 3.3 V
  • VOUT = 1.2 V Application Curves

TPS53317A C016_SLUSAK4.png Figure 40. Bode Plot No Load
TPS53317A C017_SLUSAK4.png Figure 41. Bode Plot Full Load