SLUSC63A November 2015 – December 2015 TPS53317A
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS53317A device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with both sink and source capability. The device employs D-CAP+ mode operation that provides ease-of-use, low external component count and fast transient response.
This DDR4 application requires a tight load tolerance, fast transient response, and sinking current capability, the design uses a non-droop PWM configuration.
Because this DDR4 application requires a tight load tolerance, fast transient response, and sinking current capability, the design uses a non-droop PWM configuration. Choose 600-kHz switching frequency due to the duty cycle and minimim off-time of the device, and set an overcurrent (OC) valley limit of 5.4 A due to the maximum load requirement of 2.5 A. Referring to Table 1 select an RMODE value of 68 kΩ.
Smaller inductor values have better transient performance but higher ripple and lower efficiency. High values have the opposite characteristics. It is common practice to limit the ripple current to 30% to 50% of the maximum current. Choose 50% to allow use of a smaller inductor for faster transient performance.
Because this device operates in DCAP+ mode, the frequency and duty cycle vary based on the input voltage, the output voltage and load. With a 2.5-A load, a 1.2-V input voltage and 0.60 V output voltage, fSW is experimentally measured at approximately 800 kHz and duty cycle of 0.55. Therefore L is calculated as shown in Equation 10.
Choose the closest standard value, 0.25 µH.
Use Equation 10 to calculate the output capacitance for a desired maximum overshoot.
Choose a value of 30 mV to account for normal output voltage ripple.
Use Equation 12 to calculate the necessary output capacitance for a desired maximum undershoot.
Again, choose 30 mV to account for normal output voltage ripple.
The undershoot requirements determine, so there must be a minimum of 157.6 µF. Because this is a DDR application where size is also a consideration, this design uses only ceramic capacitors. To account for voltage de-rating of capacitors and provide additional margin, this design includes eleven 22-µF output capacitors.
This design requires sufficient input capacitance to filter the input current from the host source. Use Equation 14 to calculate the necessary input capacitance.
As with the output capacitance selection, this design accounts for voltage de-rating of capacitors and provides additional margin, using four 22-µF input capacitors.
In order to achieve stable operation, the crossover frequency should be less than 1/5 of the switching frequency.
Account for capacitor de-rating here and set the value of COUT to 160 µF, so that Equation 17 is true.
Choose an RC value of 3.9 kΩ. Determine CC by choosing the value of the zero created by RC and CC. Using the relationship described in Equation 18.
Because CC >> CP , set the pole to be two times the switching frequency as described in Equation 20.
To boost the gain margin, set CP to 33 pF.
As described in Table 1, connect a 0.22-µF capacitor from the VREF pin to GND and connect a 0.1-µF bootstrap capacitor from the SW pin to the BST pin. Because the PGOOD pin is open drain, connect a pullup resistor between it and the 5-V rail.
|VIN = 1.2||fSW = 600 kHz|