0.9V-6V Input, 6-A Output, D-CAP+ Mode, SWIFT Synchronous Step-Down Converter for DDR VTT
Product details
Parameters
Package | Pins | Size
Features
- TI-Proprietary Integrated MOSFET and Packaging Technology
- Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
- External Tracking
- Minimum External Components Count
- to 6-V Conversion Voltage
- D-CAP+ Mode Architecture
- Supports All MLCC Output Capacitors and SP/POSCAP
- Selectable SKIP Mode or Forced CCM
- Optimized Efficiency at Light and Heavy Loads
- Selectable 600-kHz or 1-MHz Switching Frequency
- Selectable Overcurrent Limit (OCL)
- Overvoltage, Over-Temperature and Hiccup Undervoltage Protection
- Adjustable Output Voltage from to 2 V
- 3.5 mm × 4 mm, 20-Pin, VQFN Package
Description
The device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with bothsink and source capability. The device employs D-CAP+ mode operation that provides ease of use, low external component count and fast transient response. The device canalso be used for other point-of-load (POL) regulation applications requiring up to 6 A. Inaddition, the device supports full, 6-A, output sinking current capability with tight voltageregulation.
The device features two switching frequency settings (600 kHz and 1 MHz), integrateddroop support, external tracking capability, pre-bias startup, output soft discharge, integratedbootstrap switch, power good function, V5IN pin UVLO protection, and supports both ceramic andSP/POSCAP capacitors. It supports input voltages up to 6.0 V, and output voltages adjustable from to 2.0 V.
The device is available in the 3.5 mm × 4 mm, 20-pin, VQFNpackage (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.
For all available packages, see the orderable addendum at the end of the data sheet.Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | TPS53317A 6-A Output, D-CAP+ Mode, Synchronous Step-Down, Integrated-FET Converter for DDR Memory Termination datasheet (Rev. A) | Nov. 10, 2015 |
Application note | Point-of-Load Solutions for Data Center App Implementing VR13.HC Vccin Spec (Rev. A) | Jan. 08, 2020 | |
Technical articles | Voltage regulator features – inside the black box | May 30, 2016 | |
Technical articles | Simplifying loop compensation and poles and zeros calculations | Mar. 18, 2016 | |
User guide | Using the TPS53317AEVM-726 | Nov. 18, 2015 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The TPS53317AEVM-726 is designed to demonstrate the TPS53317A in a typical low voltage application, simulating a DDR4 enviroment, while providing a number of test points to evaluate the performance of TPS53317A. The TPS53317AEVM-726 is designed to use a 1.2-V voltage rail to produce a regulated (...)
Features
- VIN: 1.1 V - 1.3 V
- VOUT: 0.6 VDC / 6A
- Integrated synchronous buck regulator employing D-CAP+ technology
- Convenient test points for probing critical waveforms
Design tools & simulation
Reference designs
Design files
-
download PMP11399 BOM .pdf (287KB) -
download PMP11399 Assembly Drawing .pdf (531KB) -
download PMP11399 CAD Files.zip (9337KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
VQFN (RGB) | 20 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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