Top

Product details

Parameters

DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Control mode D-CAP+ Iout VTT (Max) (A) 6 Iq (Typ) (mA) 0.32 Output VREF, VTT Vin (Min) (V) 0.9 Vin (Max) (V) 6 Features Eco Mode, Fixed PWM Mode, Power Good, Tracking/Non-Tracking Mode Rating Catalog Operating temperature range (C) -40 to 125 open-in-new Find other DDR memory power ICs

Package | Pins | Size

VQFN (RGB) 20 14 mm² 4 x 3.5 open-in-new Find other DDR memory power ICs

Features

  • TI-Proprietary Integrated MOSFET and Packaging Technology
  • Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
  • External Tracking
  • Minimum External Components Count
  • to 6-V Conversion Voltage
  • D-CAP+ Mode Architecture
  • Supports All MLCC Output Capacitors and SP/POSCAP
  • Selectable SKIP Mode or Forced CCM
  • Optimized Efficiency at Light and Heavy Loads
  • Selectable 600-kHz or 1-MHz Switching Frequency
  • Selectable Overcurrent Limit (OCL)
  • Overvoltage, Over-Temperature and Hiccup Undervoltage Protection
  • Adjustable Output Voltage from to 2 V
  • 3.5 mm × 4 mm, 20-Pin, VQFN Package
open-in-new Find other DDR memory power ICs

Description

The device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with bothsink and source capability. The device employs D-CAP+ mode operation that provides ease of use, low external component count and fast transient response. The device canalso be used for other point-of-load (POL) regulation applications requiring up to 6 A. Inaddition, the device supports full, 6-A, output sinking current capability with tight voltageregulation.

The device features two switching frequency settings (600 kHz and 1 MHz), integrateddroop support, external tracking capability, pre-bias startup, output soft discharge, integratedbootstrap switch, power good function, V5IN pin UVLO protection, and supports both ceramic andSP/POSCAP capacitors. It supports input voltages up to 6.0 V, and output voltages adjustable from to 2.0 V.

The device is available in the 3.5 mm × 4 mm, 20-pin, VQFNpackage (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.

For all available packages, see the orderable addendum at the end of the data sheet.
open-in-new Find other DDR memory power ICs
Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 6
Type Title Date
* Data sheet TPS53317A 6-A Output, D-CAP+ Mode, Synchronous Step-Down, Integrated-FET Converter for DDR Memory Termination datasheet (Rev. A) Nov. 10, 2015
Technical article What’s not in the power MOSFET data sheet part 2: voltage-dependent leakage currents Jul. 23, 2021
Application note Point-of-Load Solutions for Data Center App Implementing VR13.HC Vccin Spec (Rev. A) Jan. 08, 2020
Technical article Voltage regulator features – inside the black box May 31, 2016
Technical article Simplifying loop compensation and poles and zeros calculations Mar. 18, 2016
User guide Using the TPS53317AEVM-726 Nov. 18, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
49
Description

The TPS53317AEVM-726 is designed to demonstrate the TPS53317A in a typical low voltage application, simulating a DDR4 enviroment, while providing a number of test points to evaluate the performance of TPS53317A. The TPS53317AEVM-726 is designed to use a 1.2-V voltage rail to produce a regulated (...)

Features
  • VIN: 1.1 V - 1.3 V
  • VOUT: 0.6 VDC / 6A
  • Integrated synchronous buck regulator employing D-CAP+ technology
  • Convenient test points for probing critical waveforms

Design tools & simulation

SIMULATION MODEL Download
SLUM499.ZIP (130 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
PMBus Power System for Enterprise Ethernet Switches Reference Design
PMP11399 PMP11399 is a complete PMBus power system for 3 ASIC/FPGA cores, DDR3 core memory, VTT termination, and auxiliary voltages commonly found on high-performance Ethernet Switches. The hardware is accompanied by a GUI that allows the user to perform real-time configuration and monitoring of the power (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN (RGB) 20 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos