Product details

DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Control mode D-CAP+ Iout VTT (Max) (A) 6 Iq (Typ) (mA) 0.32 Output VREF, VTT Vin (Min) (V) 0.9 Vin (Max) (V) 6 Features Eco Mode, Fixed PWM Mode, Power Good, Tracking/Non-Tracking Mode Rating Catalog Operating temperature range (C) -40 to 125
DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Control mode D-CAP+ Iout VTT (Max) (A) 6 Iq (Typ) (mA) 0.32 Output VREF, VTT Vin (Min) (V) 0.9 Vin (Max) (V) 6 Features Eco Mode, Fixed PWM Mode, Power Good, Tracking/Non-Tracking Mode Rating Catalog Operating temperature range (C) -40 to 125
VQFN (RGB) 20 14 mm² 4 x 3.5
  • TI-Proprietary Integrated MOSFET and Packaging Technology
  • Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
  • External Tracking
  • Minimum External Components Count
  • to 6-V Conversion Voltage
  • D-CAP+ Mode Architecture
  • Supports All MLCC Output Capacitors and SP/POSCAP
  • Selectable SKIP Mode or Forced CCM
  • Optimized Efficiency at Light and Heavy Loads
  • Selectable 600-kHz or 1-MHz Switching Frequency
  • Selectable Overcurrent Limit (OCL)
  • Overvoltage, Over-Temperature and Hiccup Undervoltage Protection
  • Adjustable Output Voltage from to 2 V
  • 3.5 mm × 4 mm, 20-Pin, VQFN Package
  • TI-Proprietary Integrated MOSFET and Packaging Technology
  • Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
  • External Tracking
  • Minimum External Components Count
  • to 6-V Conversion Voltage
  • D-CAP+ Mode Architecture
  • Supports All MLCC Output Capacitors and SP/POSCAP
  • Selectable SKIP Mode or Forced CCM
  • Optimized Efficiency at Light and Heavy Loads
  • Selectable 600-kHz or 1-MHz Switching Frequency
  • Selectable Overcurrent Limit (OCL)
  • Overvoltage, Over-Temperature and Hiccup Undervoltage Protection
  • Adjustable Output Voltage from to 2 V
  • 3.5 mm × 4 mm, 20-Pin, VQFN Package

The device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with bothsink and source capability. The device employs D-CAP+ mode operation that provides ease of use, low external component count and fast transient response. The device canalso be used for other point-of-load (POL) regulation applications requiring up to 6 A. Inaddition, the device supports full, 6-A, output sinking current capability with tight voltageregulation.

The device features two switching frequency settings (600 kHz and 1 MHz), integrateddroop support, external tracking capability, pre-bias startup, output soft discharge, integratedbootstrap switch, power good function, V5IN pin UVLO protection, and supports both ceramic andSP/POSCAP capacitors. It supports input voltages up to 6.0 V, and output voltages adjustable from to 2.0 V.

The device is available in the 3.5 mm × 4 mm, 20-pin, VQFNpackage (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.

For all available packages, see the orderable addendum at the end of the data sheet.

The device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with bothsink and source capability. The device employs D-CAP+ mode operation that provides ease of use, low external component count and fast transient response. The device canalso be used for other point-of-load (POL) regulation applications requiring up to 6 A. Inaddition, the device supports full, 6-A, output sinking current capability with tight voltageregulation.

The device features two switching frequency settings (600 kHz and 1 MHz), integrateddroop support, external tracking capability, pre-bias startup, output soft discharge, integratedbootstrap switch, power good function, V5IN pin UVLO protection, and supports both ceramic andSP/POSCAP capacitors. It supports input voltages up to 6.0 V, and output voltages adjustable from to 2.0 V.

The device is available in the 3.5 mm × 4 mm, 20-pin, VQFNpackage (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.

For all available packages, see the orderable addendum at the end of the data sheet.

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Technical documentation

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Type Title Date
* Data sheet TPS53317A 6-A Output, D-CAP+ Mode, Synchronous Step-Down, Integrated-FET Converter for DDR Memory Termination datasheet (Rev. A) 10 Nov 2015
Technical article 3 quiescent-current (Iq) specifications you need to understand 12 Nov 2021
Application note Point-of-Load Solutions for Data Center App Implementing VR13.HC Vccin Spec (Rev. A) 08 Jan 2020
Technical article Voltage regulator features – inside the black box 31 May 2016
Technical article Simplifying loop compensation and poles and zeros calculations 18 Mar 2016
User guide Using the TPS53317AEVM-726 18 Nov 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TPS53317AEVM-726 — Synchronous Step-Down Converter for DDR VTT Evaluation Module

The TPS53317AEVM-726 is designed to demonstrate the TPS53317A in a typical low voltage application, simulating a DDR4 enviroment, while providing a number of test points to evaluate the performance of TPS53317A. The TPS53317AEVM-726 is designed to use a 1.2-V voltage rail to produce a regulated (...)

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Simulation model

TPS53317A PSpice Transient Model

SLUM499.ZIP (130 KB) - PSpice Model
Reference designs

PMP11399 — PMBus Power System for Enterprise Ethernet Switches Reference Design

PMP11399 is a complete PMBus power system for 3 ASIC/FPGA cores, DDR3 core memory, VTT termination, and auxiliary voltages commonly found on high-performance Ethernet Switches. The hardware is accompanied by a GUI that allows the user to perform real-time configuration and monitoring of the power (...)
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VQFN (RGB) 20 View options

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