SLUSBP9C SEPTEMBER   2013  – June 2018 TPS53513

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  5-V LDO and VREG Start-Up
      2. 7.3.2  Enable, Soft Start, and Mode Selection
      3. 7.3.3  Frequency Selection
      4. 7.3.4  D-CAP3 Control and Mode Selection
        1. 7.3.4.1 D-CAP3 Mode
        2. 7.3.4.2 Sample and Hold Circuitry
        3. 7.3.4.3 Adaptive Zero-Crossing
      5. 7.3.5  Power-Good
      6. 7.3.6  Current Sense and Overcurrent Protection
      7. 7.3.7  Overvoltage and Undervoltage Protection
      8. 7.3.8  Out-Of-Bounds Operation
      9. 7.3.9  UVLO Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Choose the Switching Frequency
        2. 8.2.2.2 Choose the Operation Mode
        3. 8.2.2.3 Choose the Inductor
        4. 8.2.2.4 Choose the Output Capacitor
        5. 8.2.2.5 Determine the Value of R1 and R2
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range, VREG = 5 V, EN = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVDD VDD bias current TA = 25°C, No load
Power conversion enabled (no switching)		 1350 1850 µA
IVDDSTBY VDD standby current TA = 25°C, No load
Power conversion disabled		 850 1150 µA
IVIN(leak) VIN leakage current VEN = 0 V 0.5 µA
VREF OUTPUT
VVREF Reference voltage FB w/r/t GND, TA = 25°C 597 600 603 mV
VVREFTOL Reference voltage tolerance FB w/r/t GND, TJ = 0°C to 85°C –0.6% 0.5%
FB w/r/t GND, TJ = –40°C to 85°C –0.7% 0.5%
OUTPUT VOLTAGE
IFB FB input current VFB = 600 mV 50 100 nA
IVODIS VO discharge current VVO = 0.5 V, Power Conversion Disabled 10 12 15 mA
SMPS FREQUENCY
fSW VO switching frequency(2) VIN = 12 V, VVO = 3.3 V, RDR< 0.041 250 kHz
VIN = 12 V, VVO = 3.3 V, RDR = 0.096 300
VIN = 12 V, VVO = 3.3 V, RDR = 0.16 400
VIN = 12 V, VVO = 3.3 V, RDR = 0.229 500
VIN = 12 V, VVO = 3.3 V, RDR = 0.297 600
VIN = 12 V, VVO = 3.3 V, RDR = 0.375 750
VIN = 12 V, VVO = 3.3 V, RDR = 0.461 850
VIN = 12 V, VVO = 3.3 V, RDR> 0.557 1000
tON(min) Minimum on-time TA = 25°C(1) 60 ns
tOFF(min) Minimum off-time TA = 25°C 175 240 310 ns
INTERNAL BOOTSTRAP SW
VF Forward Voltage VVREG–VBST, TA = 25°C, IF = 10 mA 0.15 0.25 V
IVBST VBST leakage current TA = 25°C, VVBST = 33 V, VSW = 28 V 0.01 1.5 µA
LOGIC THRESHOLD
VENH EN enable threshold voltage 1.3 1.4 1.5 V
VENL EN disable threshold voltage 1.1 1.2 1.3 V
VENHYST EN hysteresis voltage 0.22 V
VENLEAK EN input leakage current –1 0 1 µA
SOFT START
tSS Soft-start time 1 ms
PGOOD COMPARATOR
VPGTH VDDQ PGOOD threshold PGOOD in from higher 104% 108% 111%
PGOOD in from lower 89% 92% 96%
PGOOD out to higher 113% 116% 120%
PGOOD out to lower 80% 84% 87%
IPG PGOOD sink current VPGOOD = 0.5 V 4 6 mA
tPGDLY PGOOD delay time Delay for PGOOD going in 0.8 1.0 1.2 ms
Delay for PGOOD coming out 2 µs
IPGLK PGOOD leakage current VPGOOD = 5 V –1 0 1 µA
CURRENT DETECTION
RTRIP TRIP pin resistance range 20 50 kΩ
IOCL Current limit threshold, valley RTRIP = 34.8 kΩ 6.2 8.0 9.8 A
RTRIP = 25.5 kΩ 4.2 6.2 8.2
IOCLN Negative current limit threshold, valley RTRIP = 34.8 kΩ –10.5 –7.9 –5.3 A
RTRIP = 25.5 kΩ –8.7 –6.1 –3.5
VZC Zero cross detection offset 0 mV
PROTECTIONS
VVREGUVLO VREG undervoltage-lockout (UVLO) threshold voltage Wake-up 3.25 3.34 3.41 V
Shutdown 3.00 3.12 3.19
VVDDUVLO VDD UVLO threshold voltage Wake-up (default) 4.15 4.25 4.35 V
Shutdown 3.95 4.05 4.15
VOVP Overvoltage-protection (OVP) threshold voltage OVP detect voltage 116% 120% 124%
tOVPDLY OVP propagation delay With 100-mV overdrive 300 ns
VUVP Undervoltage-protection (UVP) threshold voltage UVP detect voltage 64% 68% 71%
tUVPDLY UVP delay UVP filter delay 1 ms
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold(1) Shutdown temperature 140 °C
Hysteresis 40
LDO VOLTAGE
VREG LDO output voltage VIN = 12 V, ILOAD = 10 mA 4.65 5 5.45 V
VDOVREG LDO low droop drop-out voltage VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C 365 mV
ILDOMAX LDO overcurrent limit VIN = 12 V, TA = 25°C 170 200 mA
INTERNAL MOSFETS
RDS(on)H High-side MOSFET on-resistance TA = 25°C 13.8 15.5 mΩ
RDS(on)L Low-side MOSFET on-resistance TA = 25°C 5.9 7.0 mΩ
(1) Specified by design. Not production tested.
(2) Resistor divider ratio (RDR) is described in Equation 1.