8.2.1.2.1 Selecting the Switching Frequency

The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the highest switching frequency possible since this will produce the smallest solution size. The high-switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage and the output voltage and the frequency shift limitation.

Equation 5 and Equation 6 must be used to find the maximum switching frequency for the regulator, choose the lower value of the two equations. Switching frequencies higher than these values will result in pulse-skipping or the lack of overcurrent protection during a short circuit. The typical minimum on time, t_onmin, is 130 ns for the TPS54062. For this example, the output voltage is 3.3 V and the maximum input voltage is 60 V, which allows for a maximum switch frequency up to 400 kHz when including the inductor resistance, on resistance and diode voltage in Equation 5 or Equation 6. To ensure overcurrent runaway is not a concern during short circuits in your design use Equation 6 to determine the maximum switching frequency. With a maximum input voltage of 60 V, inductor resistance of 3.7 Ω, high-side switch resistance of 2.3 Ω, low-side switch resistance of 1.1 Ω, a current limit value of 120 mA and a short circuit output voltage of 0.1 V.

The maximum switching frequency is 400 kHz in both cases and a switching frequency of 400 kHz is used. To determine the timing resistance for a given switching frequency, use Equation 4. The switching frequency is set by resistor R3 shown in Figure 20. R3 is calculated to be 298 kΩ. A standard value of 301 kΩ is used.

8.2.1.2.2 Output Inductor Selection (LO)

To calculate the minimum value of the output inductor, use Equation 7. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high inductor ripple currents will impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, the following guidelines may be used. Typically, TI recommends using KIND values in the range of 0.2 to 0.4; however, for designs using low-ESR output capacitors such as ceramics and low output currents, a value as high as KIND = 1 may be used. In a wide-input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this design example, use KIND = 0.8 and the minimum inductor value is calculated to be 195 µH. For this design, a near standard value was chosen: 220 µH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 9 and Equation 10.

For this design, the RMS inductor current is 50 mA and the peak inductor current is 68 mA. The chosen inductor is a Coilcraft LPS4018-224ML. It has a saturation current rating of 235 mA and an RMS current rating of 200 mA. As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of the regulator but allow for a lower inductance value. The current flowing through the inductor is the inductor ripple current plus the output current. During power-up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current.

Equation 7.

Equation 8.

Equation 9.

Equation 10.

8.2.1.2.3 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor will determine the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also will temporarily not be able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 14 shows the minimum output capacitance necessary to accomplish this. Where ΔIout is the change in output current, ƒ_sw is the regulators switching frequency and ΔVout is the allowable change in the output voltage.

For this example, the transient load response is specified as a 4% change in Vout for a load step from 0A (no load) to 50 mA (full load). For this example, ΔI_OUT = 0.05-0 = 0.05 and ΔV_OUT = 0.04 × 3.3 = 0.132.

Using these numbers gives a minimum capacitance of 1.89 µF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into account. The low-side FET of the regulator emulates a diode so it can not sink current so any stored energy in the inductor will produce an output voltage overshoot when the load current rapidly decreases, see Figure 26. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 13 is used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L_O is the value of the inductor, I_OH is the output current under heavy load, I_OL is the output under light-load, VF is the final peak output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step will be from 50 mA to 0A. The output voltage will increase during this load transition and the stated maximum in our specification is 4% of the output voltage. This will make VF = 1.04 × 3.3 = 3.432 V. Vi is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 14 yields a minimum capacitance of 0.619 µF.

Equation 12 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where f_SW is the switching frequency, V_RIPPLE is the maximum allowable output voltage ripple, and I_RIPPLE is the inductor ripple current. Equation 13 yields 0.671 µF. Equation 15 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 15 indicates the ESR should be less than 0.466 Ω.

The most stringent criteria for the output capacitor is 1.89 µF of capacitance to keep the output voltage in regulation during an load transient.

Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which will increase this minimum value. For this example, 10-µF, 10V X5R ceramic capacitor with 0.003 Ω of ESR will be used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current.

Equation 11 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 11 yields 10.23 mA.

Equation 11.

Equation 12.

Equation 13.

Equation 14.

Equation 15.

8.2.1.2.4 Input capacitor

The TPS54062 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 1µF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a RMS current rating greater than the maximum RMS input current of the TPS54062. The input RMS current can be calculated using Equation 16. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 100-V voltage rating is required to support the maximum input voltage. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using rearranging Equation 17.

Using the design example values, Ioutmax = 50 mA, C_IN = 2.2 µF, ƒ_SW = 400 kHz, yields an input voltage ripple of 14.2 mV and a RMS input ripple current of 24.6 mA.

Equation 16.

Equation 17.

8.2.1.2.5 Bootstrap Capacitor Selection

A 0.01-µF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. TI recommends using a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or higher voltage rating.

8.2.1.2.6 Under Voltage Lock Out Set Point

The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54062. The UVLO has two thresholds, one for power-up when the input voltage is rising and one for power-down or brownouts when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 7.88 V (enabled). After the regulator starts switching, it should continue to do so until the input voltage falls below 6.66 V (UVLO stop). The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example application, a 174-kΩ resistor between Vin and EN and a 31.6-kΩ resistor between EN and ground are required to produce the 7.88 and 6.66 volt start and stop voltages.

8.2.1.2.7 Output Voltage and Feedback Resistors Selection

For the example design, 10-kΩ was selected for R_LS. Using Equation 1, R_HS is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ.

8.2.1.2.8 Closing the Loop

There are several methods used to compensate DC - DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope compensation is ignored, the actual cross over frequency will usually be lower than the crossover frequency used in the calculations. This method assume the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. Use SwitcherPro™ software for a more accurate design.

To get started, the modulator pole, fpole, and the ESR zero, fzero must be calculated using Equation 18 and Equation 19. For Cout, use a derated value of 8.9 µF. Use Equation 20 and Equation 21, to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpole is 271 Hz and fzero is 5960 kHz.

Equation 20 is the geometric mean of the modulator pole and the ESR zero and Equation 21 is the mean of modulator pole and the switching frequency. Equation 20 yields 40.29 kHz and Equation 21 gives 7.36 kHz. Use a frequency near the lower value of Equation 20 or Equation 21 for an initial crossover frequency.

For this example, fco is 7.8 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.

To determine the compensation resistor, R4, use Equation 22. Assume the power stage transconductance, gmps, is 0.65 A/V. The output voltage, Vo, reference voltage, V_REF, and amplifier transconductance, gmea, are 3.3 V, 0.8 V and 102 µS, respectively.

R4 is calculated to be 27.1 kΩ, use the nearest standard value of 27.4 kΩ. Use Equation 23 to set the compensation zero to the modulator pole frequency. Equation 23 yields 0.0214 µF for compensating capacitor C5, a 0.022 µF is used on the board. Use the larger value of Equation 24 and Equation 25 to calculate the C6 value, to set the compensation pole. Equation 25yields 29 pF so the nearest standard of 27 pF is used.

Equation 18.

Equation 19.

Equation 20.

Equation 21.

Equation 22.

Equation 23.

Equation 24.

Equation 25.

8.2.2.2.1 Closing the Feedback Loop

The method presented here is easy to calculate and includes the effect of the slope compensation that is internal to the device. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. Once the output components are determined, use the equations below to close the feedback loop. A current mode controlled power supply operating in DCM has a transfer function which has an ESR zero and pole as shown in Equation 39. To calculate the current mode power stage gain, first calculate, Kdcm, DCM gain, and Fm, modulator gain, in Equation 40 and Equation 41. Kdcm and Fm are 26.3 and 1.34 respectively. The location of the pole and ESR zero are calculated using Equation 42 and Equation 43 . The pole and zero are 67 Hz and 2 MHz, respectively. Use the lower value of Equation 44 and Equation 45 as a starting point for the crossover frequency. Equation 44 is the geometric mean of the power stage pole and the ESR zero and Equation 45 is the mean of power stage pole and the switching frequency. The crossover frequency is chosen as 2.5 kHz from Equation 45.

To determine the compensation resistor, R_COMP, use Equation 46. Assume the power stage transconductance, gmps, is 0.65 A/V. The output voltage, V_O, reference voltage, V_REF, and amplifier transconductance, gmea, are 3.3 V, 0.8 V and 102 µS, respectively. R_COMP is calculated to be 32.7 kΩ, use the nearest standard value of 32.4 kΩ. Use Equation 47 to set the compensation zero to the modulator pole frequency. Equation 47 yields 139 nF for compensating capacitor C_COMP, a 330 nF is used on the board. Use the larger value of Equation 48 or Equation 49 to calculate the C_POLE, to set the compensation pole. Equation 49 yields 98 pF so the nearest standard of 100 pF is used.

Equation 39.

Equation 40.

Equation 41.

Equation 42.

Equation 43.

Equation 44.

Equation 45.

Equation 46.

Equation 47.

Equation 48.

Equation 49.