SLVS834B July   2008  – June 2019 TPS5450-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic and Efficiency Curve
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Dissipation Ratings
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Frequency
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Enable (ENA) and Internal Slow Start
      4. 7.3.4  Undervoltage Lockout (UVLO)
      5. 7.3.5  Output Feedback (VSENSE) and Internal Compensation
      6. 7.3.6  Voltage Feedforward
      7. 7.3.7  Pulse-Width-Modulation (PWM) Control
      8. 7.3.8  Overcurrent Limiting
      9. 7.3.9  Overvoltage Protection
      10. 7.3.10 Thermal Shutdown
  8. 8 Application Information
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Boost Capacitor (BOOT)
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Output Filter Components
          1. 8.2.2.5.1 Inductor Selection
          2. 8.2.2.5.2 Capacitor Selection
        6. 8.2.2.6  Output Voltage Setpoint
        7. 8.2.2.7  Boot Capacitor
        8. 8.2.2.8  Catch Diode
        9. 8.2.2.9  Output Voltage Limitations
        10. 8.2.2.10 Internal Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Examples
    3. 9.3 Thermal Calculations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Development Support
      1. 10.2.1 Custom Design With WEBENCH® Tools
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Thermal Information

THERMAL METRIC(1) TPS5450-Q1 UNITS
DDA
8 PINS
θJA Junction-to-ambient thermal resistance(2) 48.2 °C/W
θJCtop Junction-to-case (top) thermal resistance(3) 47.1 °C/W
θJB Junction-to-board thermal resistance(4) 22.5 °C/W
ψJT Junction-to-top characterization parameter(5) 5.4 °C/W
ψJB Junction-to-board characterization parameter(6) 22.4 °C/W
θJCbot Junction-to-case (bottom) thermal resistance(7) 2.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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