SLUSCI9A August   2016  – September 2017 TPS549D22

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 40-A FET
      2. 7.3.2 On-Resistance
      3. 7.3.3 Package Size, Efficiency and Thermal Performance
      4. 7.3.4 Soft-Start Operation
      5. 7.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
      6. 7.3.6 EN_UVLO Pin Functionality
      7. 7.3.7 Fault Protections
        1. 7.3.7.1 Current Limit (ILIM) Functionality
        2. 7.3.7.2 VDD Undervoltage Lockout (UVLO)
        3. 7.3.7.3 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
        4. 7.3.7.4 Out-of-Bounds Operation
        5. 7.3.7.5 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 DCAP3 Control Topology
      2. 7.4.2 DCAP Control Topology
    5. 7.5 Programming
      1. 7.5.1 Programmable Pin-Strap Settings
        1. 7.5.1.1 Address Selection (ADDR) Pin
        2. 7.5.1.2 VSEL Pin
        3. 7.5.1.3 DCAP3 Control and Mode Selection
        4. 7.5.1.4 Application Workaround to Support 4-ms and 8-ms SS Settings
      2. 7.5.2 Programmable Analog Configurations
        1. 7.5.2.1 RSP/RSN Remote Sensing Functionality
          1. 7.5.2.1.1 Output Differential Remote Sensing Amplifier
        2. 7.5.2.2 Power Good (PGOOD Pin) Functionality
      3. 7.5.3 PMBus Programming
        1. 7.5.3.1 TPS549D22 Limitations to the PMBUS Specifications
        2. 7.5.3.2 Slave Address Assignment
        3. 7.5.3.3 PMBUS Address Selection
        4. 7.5.3.4 Supported Formats
          1. 7.5.3.4.1 Direct Format — Write
          2. 7.5.3.4.2 Combined Format — Read
        5. 7.5.3.5 Stop Separated Reads
        6. 7.5.3.6 Supported PMBUS Commands and Registers
      4. 7.5.4 Register Maps
        1. 7.5.4.1  OPERATION Register (address = 1h)
        2. 7.5.4.2  ON_OFF_CONFIG Register (address = 2h)
        3. 7.5.4.3  CLEAR FAULTS (address = 3h)
        4. 7.5.4.4  WRITE PROTECT (address = 10h)
        5. 7.5.4.5  STORE_DEFAULT_ALL (address = 11h)
        6. 7.5.4.6  RESTORE_DEFAULT_ALL (address = 12h)
        7. 7.5.4.7  CAPABILITY (address = 19h)
        8. 7.5.4.8  VOUT_MODE (address = 20h)
        9. 7.5.4.9  VOUT_COMMAND (address = 21h)
        10. 7.5.4.10 VOUT_MARGIN_HIGH (address = 25h)
        11. 7.5.4.11 VOUT_MARGIN_LOW (address = 26h)
        12. 7.5.4.12 STATUS_BYTE (address = 78h)
        13. 7.5.4.13 STATUS_WORD (High Byte) (address = 79h)
        14. 7.5.4.14 STATUS_VOUT (address = 7Ah)
        15. 7.5.4.15 STATUS_IOUT (address = 7Bh)
        16. 7.5.4.16 STATUS_CML (address = 7Eh)
        17. 7.5.4.17 MFR_SPECIFIC_00 (address = D0h)
        18. 7.5.4.18 MFR_SPECIFIC_01 (address = D1h)
        19. 7.5.4.19 MFR_SPECIFIC_02 (address = D2h)
        20. 7.5.4.20 MFR_SPECIFIC_03 (address = D3h)
        21. 7.5.4.21 MFR_SPECIFIC_04 (address = D4h)
        22. 7.5.4.22 MFR_SPECIFIC_06 (address = D6h)
        23. 7.5.4.23 MFR_SPECIFIC_07 (address = D7h)
        24. 7.5.4.24 MFR_SPECIFIC_44 (address = FCh)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: TPS549D22 1.5-V to 16-V Input, 1-V Output, 40-A Converter
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency Selection
        3. 8.2.2.3  Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
          1. 8.2.2.4.1 Minimum Output Capacitance to Ensure Stability
          2. 8.2.2.4.2 Response to a Load Transient
          3. 8.2.2.4.3 Output Voltage Ripple
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Bootstrap Capacitor Selection
        7. 8.2.2.7  BP Pin
        8. 8.2.2.8  R-C Snubber and VIN Pin High-Frequency Bypass
        9. 8.2.2.9  Optimize Reference Voltage (VSEL)
        10. 8.2.2.10 MODE Pin Selection
        11. 8.2.2.11 ADDR Pin Selection
        12. 8.2.2.12 Overcurrent Limit Design
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Custom Design With WEBENCH® Tools
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 13Package Option Addendum
    1. 13.1 Packaging Information
    2. 13.2 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RVF|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Input Voltage Range (PVIN): 1.5 V to 16 V
  • Input Bias Voltage (VDD) Range: 4.5 V to 22 V
  • Output Voltage Range: 0.6 V to 5.5 V
  • Integrated, 2.9-mΩ and 1.2-mΩ Power MOSFETs With 40-A Continuous Output Current
  • Voltage Reference 0.6 V to 1.2 V in 50-mV Steps Using VSEL Pin
  • ±0.5%, 0.9-VREF Tolerance Range: –40°C to +125°C Junction Temperature
  • True Differential Remote Sense Amplifier
  • D-CAP3™ Control Loop
  • Adaptive On-Time Control with 8 PMBusTM Frequency: 315 kHz, 425 kHz, 550 kHz, 650 kHz, 825 kHz, 900 kHz, 1.025 MHz, 1.125 MHz
  • Temperature Compensated and Programmable Current Limit with RILIM and OC Clamp
  • Choice of Hiccup or Latch-Off OVP or UVP
  • VDD UVLO External Adjustment by Precision EN
  • Prebias Start-up Support
  • Eco-mode™ and FCCM Selectable
  • Full Suite of Fault Protection and PGOOD
  • Standard VOUT_COMMAND and VOUT_MARGIN (HIGH and LOW)
  • Pin-Strapping and On-the-Fly Programming
  • Fault Reporting and Warning
  • NVM Backup for Selected Commands
  • 1-MHz PMBus with PEC and SMB_ALRT#
  • Create a Custom Design Using the TPS549D22 With the WEBENCH® Power Designer

2 Applications

  • Enterprise Storage, SSD, NAS
  • Wireless and Wired Communication Infrastructure
  • Industrial PCs, Automation, ATE, PLC, Video Surveillance
  • Enterprise Server, Switches, Routers
  • ASIC, SoC, FPGA, DSP Core, and I/O Rails

3 Description

The TPS549D22 device is a compact single buck converter with adaptive on-time, D-CAP3 mode control. It is designed for high accuracy, high efficiency, fast transient response, ease-of-use, low external component count and space-conscious power systems.

This device features full differential sense, TI integrated FETs with a high-side on-resistance of 2.9 mΩ and a low-side on-resistance of 1.2 mΩ. The device also features accurate 0.5%, 0.9-V reference with an ambient temperature range between –40°C and +125°C. Competitive features include: very low external component count, accurate load regulation and line regulation, auto-skip or FCCM mode operation, and internal soft-start control.

The TPS549D22 device is available in 7-mm × 5-mm, 40-pin, LQFN-CLIP (RVF) package (RoHs exempt).

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS549D22 LQFN-CLIP (40) 7.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Application

TPS549D22 simp_app_SLUSCI9.gif