SLUSCI9A August 2016 – September 2017 TPS549D22
Consider these layout guidelines before starting a layout work using TPS549D22.
Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the reflow process can affect electrical performance. Figure 70 shows the recommended reflow oven thermal profile. Proper post-assembly cleaning is also critical to device performance. See the Application Report, QFN/SON PCB Attachment, (SLUA271) for more information.
|RAMP UP AND RAMP DOWN|
|rRAMP(up)||Average ramp-up rate, TS(max) to TP||3||°C/s|
|rRAMP(down)||Average ramp-down rate, TP to TS(max)||6||°C/s|
|tS||Pre-heat time, TS(min) to TS(max)||60||180||s|
|tL||Time maintained above liquidus temperature, TL||60||150||s|
|tP||Time maintained within 5°C of peak temperature, TP||20||40||s|
|t25P||Total time from 25°C to peak temperature, TP||480||s|