SLUSCI9A August   2016  – September 2017 TPS549D22


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 40-A FET
      2. 7.3.2 On-Resistance
      3. 7.3.3 Package Size, Efficiency and Thermal Performance
      4. 7.3.4 Soft-Start Operation
      5. 7.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
      6. 7.3.6 EN_UVLO Pin Functionality
      7. 7.3.7 Fault Protections
        1. Current Limit (ILIM) Functionality
        2. VDD Undervoltage Lockout (UVLO)
        3. Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
        4. Out-of-Bounds Operation
        5. Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 DCAP3 Control Topology
      2. 7.4.2 DCAP Control Topology
    5. 7.5 Programming
      1. 7.5.1 Programmable Pin-Strap Settings
        1. Address Selection (ADDR) Pin
        2. VSEL Pin
        3. DCAP3 Control and Mode Selection
        4. Application Workaround to Support 4-ms and 8-ms SS Settings
      2. 7.5.2 Programmable Analog Configurations
        1. RSP/RSN Remote Sensing Functionality
          1. Output Differential Remote Sensing Amplifier
        2. Power Good (PGOOD Pin) Functionality
      3. 7.5.3 PMBus Programming
        1. TPS549D22 Limitations to the PMBUS Specifications
        2. Slave Address Assignment
        3. PMBUS Address Selection
        4. Supported Formats
          1. Direct Format — Write
          2. Combined Format — Read
        5. Stop Separated Reads
        6. Supported PMBUS Commands and Registers
      4. 7.5.4 Register Maps
        1.  OPERATION Register (address = 1h)
        2.  ON_OFF_CONFIG Register (address = 2h)
        3.  CLEAR FAULTS (address = 3h)
        4.  WRITE PROTECT (address = 10h)
        5.  STORE_DEFAULT_ALL (address = 11h)
        6.  RESTORE_DEFAULT_ALL (address = 12h)
        7.  CAPABILITY (address = 19h)
        8.  VOUT_MODE (address = 20h)
        9.  VOUT_COMMAND (address = 21h)
        10. VOUT_MARGIN_HIGH (address = 25h)
        11. VOUT_MARGIN_LOW (address = 26h)
        12. STATUS_BYTE (address = 78h)
        13. STATUS_WORD (High Byte) (address = 79h)
        14. STATUS_VOUT (address = 7Ah)
        15. STATUS_IOUT (address = 7Bh)
        16. STATUS_CML (address = 7Eh)
        17. MFR_SPECIFIC_00 (address = D0h)
        18. MFR_SPECIFIC_01 (address = D1h)
        19. MFR_SPECIFIC_02 (address = D2h)
        20. MFR_SPECIFIC_03 (address = D3h)
        21. MFR_SPECIFIC_04 (address = D4h)
        22. MFR_SPECIFIC_06 (address = D6h)
        23. MFR_SPECIFIC_07 (address = D7h)
        24. MFR_SPECIFIC_44 (address = FCh)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: TPS549D22 1.5-V to 16-V Input, 1-V Output, 40-A Converter
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Custom Design With WEBENCH® Tools
        2.  Switching Frequency Selection
        3.  Inductor Selection
        4.  Output Capacitor Selection
          1. Minimum Output Capacitance to Ensure Stability
          2. Response to a Load Transient
          3. Output Voltage Ripple
        5.  Input Capacitor Selection
        6.  Bootstrap Capacitor Selection
        7.  BP Pin
        8.  R-C Snubber and VIN Pin High-Frequency Bypass
        9.  Optimize Reference Voltage (VSEL)
        10. MODE Pin Selection
        11. ADDR Pin Selection
        12. Overcurrent Limit Design
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Custom Design With WEBENCH® Tools
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 13Package Option Addendum
    1. 13.1 Packaging Information
    2. 13.2 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RVF|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

Consider these layout guidelines before starting a layout work using TPS549D22.

  • It is absolutely critical that all GND pins, including AGND (pin 30), DRGND (pin 29), and PGND (pins 13, 14, 15, 16, 17, 18, 19, and 20) are connected directly to the thermal pad underneath the device via traces or plane.
  • Include as many thermal vias as possible to support a 40-A thermal operation. For example, a total of 35 thermal vias are used (outer diameter of 20 mil) in the available for purchase at
  • Placed the power components (including input/output capacitors, output inductor and device) on one side of the PCB (solder side). Insert at least two inner layers (or planes) connected to the power ground, in order to shield and isolate the small signal traces from noisy power lines.
  • Place the VIN pin decoupling capacitors as close as possible to the PVIN and PGND pins to minimize the input AC current loop. Place a high-frequency decoupling capacitor (with a value between 1 nF and 0.1 µF) as close to the PVIN pin and PGND pin as the spacing rule allows. This placement helps suppress the switch node ringing.
  • Place VDD and BP decoupling capacitors as close to the device pins as possible. Do not use PVIN plane connection for the VDD pin. Separate the VDD signal from the PVIN signal by using separate trace connections. Provide GND vias for each decoupling capacitor and make the loop as small as possible.
  • Ensure that the PCB trace defined as switch node (which connects the SW pins and up-stream of the output inductor) are as short and wide as possible. In the EVM design, the SW trace width is 200 mil. Use a separate via or trace to connect SW node to snubber and bootstrap capacitor. Do not combine these connections.
  • Place all sensitive analog traces and components (including VOSNS, RSP, RSN, ILIM, MODE, VSEL and ADDR) far away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise coupling. In addition, place MODE, VSEL and ADDR programming resistors near the device pins.
  • The RSP and RSN pins operate as inputs to a differential remote sense amplifier that operates with very high impedance. It is essential to route the RSP and RSN pins as a pair of diff-traces in Kelvin-sense fashion. Route them directly to either the load sense points (+ and –) or the output bulk capacitors. The internal circuit uses the VOSNS pin for on-time adjustment. It is critical to tie the VOSNS pin directly tied to VOUT (load sense point) for accurate output voltage result.

Layout Example

TPS549D22 evm_top_view.gif Figure 63. EVM Top View
TPS549D22 evm_inner_layer1.gif Figure 65. EVM Inner Layer 1
TPS549D22 evm_layer6.gif Figure 67. EVM Inner Layer 3
TPS549D22 evm_bottom_layer.gif Figure 69. EVM Bottom Layer
TPS549D22 evm_layer3.gif Figure 64. EVM Top Layer
TPS549D22 evm_layer5.gif Figure 66. EVM Inner Layer 2
TPS549D22 evm_layer4.gif Figure 68. EVM Inner Layer 4

Mounting and Thermal Profile Recommendation

Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the reflow process can affect electrical performance. Figure 70 shows the recommended reflow oven thermal profile. Proper post-assembly cleaning is also critical to device performance. See the Application Report, QFN/SON PCB Attachment, (SLUA271) for more information.

TPS549D22 mech_thermal_profile_slusc81.gif Figure 70. Recommended Reflow Oven Thermal Profile

Table 41. Recommended Thermal Profile Parameters

rRAMP(up) Average ramp-up rate, TS(max) to TP 3 °C/s
rRAMP(down) Average ramp-down rate, TP to TS(max) 6 °C/s
TS Pre-heat temperature 150 200 °C
tS Pre-heat time, TS(min) to TS(max) 60 180 s
TL Liquidus temperature 217 °C
TP Peak temperature 260 °C
tL Time maintained above liquidus temperature, TL 60 150 s
tP Time maintained within 5°C of peak temperature, TP 20 40 s
t25P Total time from 25°C to peak temperature, TP 480 s