SLVSEQ0A May   2019  – March 2020 TPS54A24

PRODUCTION DATA.  

  1. Features
  2. Applications
    1.     Simplified Schematic
  3. Description
    1.     Efficiency (VIN = 12 V, fSW = 500 kHz)
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Conduction Mode Operation (CCM)
      3. 7.3.3  VIN Pins and VIN UVLO
      4. 7.3.4  Voltage Reference and Adjusting the Output Voltage
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Soft Start and Tracking
      8. 7.3.8  Safe Start-Up Into Prebiased Outputs
      9. 7.3.9  Power Good
      10. 7.3.10 Sequencing (SS/TRK)
      11. 7.3.11 Adjustable Switching Frequency (RT Mode)
      12. 7.3.12 Synchronization (CLK Mode)
      13. 7.3.13 Bootstrap Voltage and 100% Duty Cycle Operation (BOOT)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-Side MOSFET Overcurrent Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Output Voltage Resistors Selection
        7. 8.2.2.7  Soft-Start Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Setpoint
        9. 8.2.2.9  Bootstrap Capacitor Selection
        10. 8.2.2.10 PGOOD Pullup Resistor
        11. 8.2.2.11 Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Enable and Adjustable UVLO

The EN pin provides on/off control of the device. Once the EN pin voltage exceeds its threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low operating current state. The EN pin has an internal pullup current source, Ip, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, an open drain or open collector output logic can be interfaced with the pin.

An external resistor divider can be added from VIN to the EN pin for adjustable UVLO and hysteresis as shown in Figure 27. The EN pin has a small pullup current Ip which sets the default state of the pin to enable when no external components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using Equation 2 and Equation 3. When using the adjustable UVLO function, 500 mV or greater hysteresis is recommended. For applications with very slow input voltage slew rate, a capacitor can be placed from the EN pin to ground to filter any glitches on the input voltage.

TPS54A24 fd_adj_uvlo_slvseq0-tps54A24.gifFigure 27. Adjustable UVLO Using EN
Equation 2. TPS54A24 RENT_SCO3.gif

vertical spacer

Equation 3. TPS54A24 RENB_SCO3.gif