SLVSFQ8A Data sheet

SLVSFQ8A December 2020 – December 2021 TPS552882-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RPM|26
- MPQF533A

Thermal pad, mechanical data (Package|Pins)

RPM|26
- QFND631

Orderable Information

6.5 Electrical Characteristics

T_J = -40°C to 125°C, V_IN = 12 V and V_OUT = 20 V. Typical values are at T_J = 25°C, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY
V_IN	Input voltage range		2.7		36	V
V_{VIN_UVLO}	Under voltage lockout threshold	V_IN rising	2.8	2.9	3.0	V
V_{VIN_UVLO}	Under voltage lockout threshold	V_IN falling	2.6	2.65	2.7	V
I_Q	Quiescent current into the VIN pin	IC enabled, no load, no switching. V_IN = 3 V to 24 V, V_OUT = 0.8 V, V_FB = V_REF + 0.1 V, R_FSW=100 kΩ, T_J up to 125°C		760	860	µA
I_Q	Quiescent current into the VOUT pin	IC enabled, no load, no switching, V_IN = 2.9 V, V_OUT = 3 V to 20 V, V_FB = V_REF + 0.1 V, R_FSW=100 kΩ, T_J up to 125°C		760	860	µA
I_SD	Shutdown current into VIN pin	IC disabled, V_IN = 2.9 V to 14 V, T_J up to 125°C		7	10	µA
V_CC	Internal regulator output	I_VCC = 50 mA, V_IN = 8 V, V_OUT = 20 V	5.0	5.2	5.4	V
V_{CC_DO}	VCC dropout	V_IN = 5.0 V, V_OUT = 20 V, I_VCC = 60 mA		200	320	mV
V_{CC_DO}	VCC dropout	V_IN = 14 V, V_OUT = 5.0 V, I_VCC = 60 mA		110	170	mV
EN/UVLO
V_{EN_H}	EN Logic high threshold	VCC = 2.7 V to 5.5 V			1.15	V
V_{EN_L}	EN Logic low threshold	VCC = 2.7 V to 5.5 V	0.4			V
V_{EN_HYS}	Enable threshold hysteresis	VCC = 2.7 V to 5.5 V	0.05	0.12		V
V_UVLO	UVLO rising threshold at the EN/UVLO pin	VCC = 3.0 V to 5.5 V	1.20	1.23	1.26	V
V_{UVLO_HYS}	UVLO threshold hysteresis	VCC = 3.0 V to 5.5 V	8	14	20	mV
I_UVLO	Sourcing current at the EN/UVLO pin	V_UVLO = 1.3 V	4.5	5	5.5	µA
OUTPUT
V_OUT	Output voltage range		0.8		22	V
V_OVP	Output overvoltage protection threshold		22.5	23.5	24.5	V
V_{OVP_HYS}	Over voltage protection hysteresis			1		V
I_{FB_LKG}	Leakage current at the FB pin	T_J up to 125°C			100	nA
I_{VOUT_LKG}	Leakage current into the VOUT pin	IC disabled, V_OUT = 20 V, V_SW2 = 0 V, T_J up to 125°C		1	20	µA
REFERENCE VOLTAGE
V_REF	Reference voltage at the FB pin		1.188	1.2	1.212	V
POWER SWITCH
R_DS(on)	Low-side MOSFET on resistance on boost side	V_OUT = 20 V, V_CC = 5.2 V		7.1		mΩ
R_DS(on)	High-side MOSFET on resistance on boost side	V_OUT = 20 V, V_CC = 5.2 V		7.6		mΩ
INTERNAL CLOCK
f_SW	Switching frequency	R_FSW = 100 kΩ	180	200	220	kHz
f_SW	Switching frequency	R_FSW = 9.09 kΩ	2000	2200	2400	kHz
t_{OFF_min}	Min. off time	Boost mode		100	145	ns
t_{ON_min}	Min. on-time	Buck mode		90	130	ns
V_FSW	Voltage at the FSW pin			1		V
CURRENT LIMIT
I_{LIM_AVG}	Average inductor current limit	R_ILIM = 20 kΩ, V_IN = 8 V, V_OUT = 20 V, f_SW = 500 kHz, FPWM	14	16.5	19	A
		R_ILIM = 20 kΩ, V_IN = 8 V, V_OUT = 20 V, f_SW = 500 kHz, PFM	14	16.5	19	A
		R_ILIM = 60 kΩ, V_IN = 5 V, V_OUT = 14 V, f_SW = 2.2 MHz, FPWM	4	5.5		A
		R_ILIM = 60 kΩ, V_IN = 5 V, V_OUT = 14 V, f_SW = 2.2 MHz, PFM	4	5.5		A
I_{LIM_PK}	Peak inductor current limit at high side	R_ILIM = 20 kΩ, V_IN = 8 V, V_OUT = 20 V, f_SW = 500 kHz, FPWM		25		A
I_{LIM_PK}	Peak inductor current limit at high side	R_ILIM = 20 kΩ, V_IN = 8 V, V_OUT = 20 V, f_SW = 500 kHz, PFM		25		A
V_ILIM	Voltage at the ILIM pin	VOUT = 3 V		0.6		V
V_SNS	Current loop regulation voltage between the ISP and ISN pins	V_ISN = 2 V to 21 V	48	50	52	mV
V_SNS		V_ISN = 2 V to 21 V	28	30	32	mV
CABLE VOLTAGE DROP COMPENSATION
V_CDC	Voltage at the CDC pin	R_CDC = 20 kΩ or floating, V_ISP – V_ISN = 50 mV	0.95	1	1.05	V
V_CDC	Voltage at the CDC pin	R_CDC = 20 kΩ or floating, V_ISP – V_ISN = 2 mV		40	75	mV
I_{FB_CDC}	FB pin sinking current	External output feedback, R_CDC = 20 kΩ, V_ISP – V_ISN = 50 mV	7.23	7.5	7.87	µA
		External output feedback, R_CDC = 20 kΩ, V_ISP – V_ISN = 0 mV		0	0.3	µA
		External output feedback, R_CDC = floating, V_ISP – V_ISN = 50 mV		0	0.3	µA
ERROR AMPLIFIER
I_SINK	COMP pin sink current	V_FB = V_REF + 400 mV, V_COMP = 1.5 V, VCC = 5 V		20		µA
I_SOURCE	COMP pin source current	V_FB = V_REF - 400 mV, V_COMP = 1.5 V, VCC = 5 V		60		µA
V_CCLPH	High clamp voltage at the COMP pin			1.8		V
V_CCLPL	Low clamp voltage at the COMP pin			0.7		V
G_EA	Error amplifier transconductance			190		µA/V
SOFT START
t_SS	Soft-start time		3	4	5	ms
DR1H GATE DRIVER
V_{DR1H_L}	Low-state voltage drop	V_DR1H – V_SW1, 100-mA sinking		0.1		V
V_{DR1H_H}	High-state voltage drop	V_BOOT1 – V_DR1H, 100-mA sourcing		0.2		V
DR1L GATE DRIVER
V_{DR1L_L}	Low-state voltage drop	100-mA sinking		0.1		V
V_{DR1L_H}	High-state voltage drop	V_CC – V_DR1L, 100-mA sourcing		0.2		V
SPREAD SPECTRUM
I_{DITH_CHG}	Dithering charge current	V_DITH/SYNC = 1.0 V, R_FSW = 49.9 kΩ; voltage rising from 0.85 V		2		µA
I_{DITH_DIS}	Dithering discharge current	V_DITH/SYNC = 1.0 V, R_FSW = 49.9 kΩ; voltage falling from 1.15 V		2		µA
V_{DITH_H}	Dither high threshold			1.07		V
V_{DITH_L}	Dither low threshold			0.93		V
SYNCHRONOUS CLOCK
V_{SNYC_H}	Sync clock high voltage threshold				1.2	V
V_{SYNC_L}	Sync clock low voltage threshold		0.4			V
t_{SYNC_MIN}	Minimum sync clock pulse width		50			ns
HICCUP
t_HICCUP	Hiccup off time			76		ms
MODE RESISTANCE DETECTION
I_MODE	Sourcing current from the MODE pin	V_MODE = 2.5 V	9	10	11	µA
V_{MODE_DT1}	Detection threshold voltage at the MODE pin		0.571	0.614	0.657	V
V_{MODE_DT2}			0.322	0.351	0.380	V
V_{MODE_DT3}			0.169	0.189	0.209	V
LOGIC INTERFACE
I_{PG_H}	Leakage current into PG pin when outputting high impedance	V_PG = 5 V			100	nA
V_{PG_L}	Output low voltage range of the PG pin	Sinking 4-mA current		0.1	0.2	V
I_{CC_H}	Leakage current into CC pin when outputting high impedance	V_CC = 5 V			100	nA
V_{CC_L}	Output low voltage range of the CC pin	Sinking 4-mA current		0.1	0.2	V
PROTECTION
T_SD	Thermal shutdown threshold	T_J rising		175		°C
T_{SD_HYS}	Thermal shutdown hysteresis	T_J falling below TSD		20		°C