SLVSFP3C August   2020  – March 2022 TPS61288

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable and Start-up
      2. 8.3.2 Undervoltage Lockout (UVLO)
      3. 8.3.3 Switching Peak Current Limit
      4. 8.3.4 Overvoltage Protection
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM
      2. 8.4.2 PFM
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Setting Output Voltage
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Loop Stability
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.5 Loop Stability

The TPS61288 requires external compensation, which allows the loop response to be optimized for each application. The COMP pin is the output of the internal error amplifier. An external compensation network, comprised of resistor RC, and ceramic capacitors CC and CP, is connected to the COMP pin.

The power stage small signal loop response of constant off-time (COT) with peak current control can be modeled by Equation 7.

Equation 7. GUID-20200812-CA0I-KK6J-PBZJ-JFGBMKS5DBRQ-low.gif

where

  • D is the switching duty cycle.
  • RO is the output load resistance.
  • KCOMP is power stage trans-conductance (inductor peak current / comp voltage), which is 13.5 A/V.
Equation 8. GUID-6F7664F1-5BAE-4A6E-9B95-314061760346-low.gif

where

  • CO is output capacitor.
Equation 9. GUID-B342FC14-2708-4850-8EBD-F1DC352724BA-low.gif

where

  • RESR is the equivalent series resistance of the output capacitor.
Equation 10. GUID-FD65B6BA-5C43-455B-A7A3-347B7AD738B1-low.gif

The COMP pin is the output of the internal transconductance amplifier. Equation 11 shows the small signal transfer function of compensation network.

Equation 11. GUID-6347C096-DC49-4F1B-A772-27A87073E274-low.gif

where

  • GEA is the transconductance of the amplifier.
  • REA is the output resistance of the amplifier.
  • VREF is the reference voltage at the FB pin.
  • VOUT is the output voltage.
  • ƒCOMP1, ƒCOMP2 are the frequency of the poles of the compensation network.
  • ƒCOMZ is the zero's frequency of the compensation network.

The next step is to choose the loop crossover frequency, ƒC. The higher frequency that the loop gain stays above zero before crossing over, the faster the loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ.

Then set the value of RC, CC, and CP (in Figure 9-1) by following these equations.

Equation 12. GUID-20200812-CA0I-P8GW-NSW8-3JBCFGCZZFZL-low.gif

where

  • ƒC is the selected crossover frequency.

The value of CC can be set by Equation 13.

Equation 13. GUID-20200812-CA0I-P8TW-L9Q9-WLLFGH8RCNTH-low.gif

The value of CP can be set by Equation 14.

Equation 14. GUID-20200812-CA0I-MSLP-RJ0H-TCJJ61QSHRL4-low.gif

If the calculated value of CP is less than 10 pF, it can be left open.

Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output voltage ringing during the line and load transient.