SLVSC20E January   2015  – October 2016 TPS62134A , TPS62134B , TPS62134C , TPS62134D


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommend Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable and Shutdown (EN)
      2. 8.3.2 Undervoltage Lockout (UVLO)
      3. 8.3.3 Soft-Start (SS) Circuitry
      4. 8.3.4 Switch Current-Limit and Short Circuit Protection
      5. 8.3.5 Output Voltage and LPM Logic Selection (VIDx and LPM)
      6. 8.3.6 Power-Good Output (PG)
      7. 8.3.7 Single-Ended Remote Sense (FBS)
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM Operation and Power Save Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Output Filter Selection
        2. Inductor Selection
        3. Output Capacitor
        4. Input Capacitor
        5. Soft-Start Capacitor
        6. Program Output Voltage with External Resistor Divider
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

  • TI recommends to place all components as close as possible to the device. Ensure that the input capacitor placement is as close as possible to the PVIN and PGND pins of the device.
  • The VOS pin is noise sensitive and must be routed short and directly to the output of the output capacitor. This routing minimizes switch node jitter and ensures reliability.
  • The direct common-ground connection of the AGND and PGND pins to the exposed thermal pad and the system ground (ground plane) is mandatory. To enhance heat dissipation of the device, the exposed thermal pad should be connected to bottom or internal layer ground planes using vias.
  • Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
  • The capacitor on the SS pin should be placed close to the device and connected directly to those pins and the AGND pin.
  • The inductor should be placed close to the SW pins, keeping this area small.
  • Finally, the ground of the output capacitor should be located close to the PGND pins of the device.
  • See Figure 19 for an example of component placement, routing, and thermal design.

Layout Example

TPS62134A TPS62134B TPS62134C TPS62134D TPS62134_PCBlayout.gif Figure 19. TPS62134x Layout Example

Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component.

The following lists three basic approaches for enhancing thermal performance:

  • Improving the power dissipation capability of the PCB design
  • Improving the thermal coupling of the component to the PCB by soldering the exposed thermal pad
  • Introducing airflow in the system

For more details on how to use the thermal parameters, see the application notes, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017), and Semiconductor and IC Package Thermal Metrics (SPRA953).