SLVSBH3B June   2016  – April 2017 TPS62135


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Schematic
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Precise Enable
      2. 9.3.2 Power Good (PG)
      3. 9.3.3 Pin-Selectable Output Voltage (VSEL and FB2)
      4. 9.3.4 MODE
      5. 9.3.5 Undervoltage Lockout (UVLO)
      6. 9.3.6 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pulse Width Modulation (PWM) Operation
      2. 9.4.2 Power Save Mode Operation (PWM/PFM)
      3. 9.4.3 100% Duty-Cycle Operation
      4. 9.4.4 HICCUP Current Limit And Short Circuit Protection (TPS62135 only)
      5. 9.4.5 Current Limit And Short Circuit Protection (TPS621351 only)
      6. 9.4.6 Soft-Start / Tracking (SS/TR)
      7. 9.4.7 Output Discharge Function (TPS62135 only)
      8. 9.4.8 Starting into a Pre-Biased Load (TPS621351 only)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Programming the Output Voltage
      2. 10.1.2 External Component Selection
      3. 10.1.3 Inductor Selection
      4. 10.1.4 Capacitor Selection
        1. Output Capacitor
        2. Input Capacitor
        3. Soft-Start Capacitor
      5. 10.1.5 Tracking Function
      6. 10.1.6 Output Filter and Loop Stability
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Application with Adjustable Output Voltage
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 10.2.2 Typical Application using VSEL and FB2
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
    3. 10.3 System Examples
      1. 10.3.1 LED Power Supply
      2. 10.3.2 Powering Multiple Loads
      3. 10.3.3 Voltage Tracking
      4. 10.3.4 Precise Soft-Start Timing
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Related Links
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description


The TPS62135 synchronous switched mode power converters are based on DCS-Control™ (Direct Control with Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of hysteretic, voltage mode and current mode control. This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage. It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors.

The DCS-Control™ topology supports PWM (Pulse Width Modulation) mode for medium and heavy load conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in continuous conduction mode. This frequency is typically about 2.5 MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the load current. Since DCS-Control™ supports both operation modes within one single building block, the transition from PWM to Power Save Mode is seamless without effects on the output voltage. An internal current limit supports nominal output currents of up to 4 A. The TPS62135x family offers both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits.

Functional Block Diagram

TPS62135 TPS621351 TPS62135_blockdiagram_adjustable.gif

The discharge switch on the VOS pin is only available in the TPS62135.

Feature Description

Precise Enable

The voltage applied at the Enable pin of the TPS62135x is compared to a fixed threshold of 0.8 V for a rising voltage. This allows to drive the pin by a slowly changing voltage and enables the use of an external RC network to achieve a power-up delay.

The Precise Enable input allows the use as a user programmable undervoltage lockout by adding a resistor divider to the input of the Enable pin.

The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The TPS62135x starts operation when the rising threshold is exceeded. For proper operation, the EN pin must be terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a shutdown current of typically 1 μA. In this mode, the internal high side and low side MOSFETs are turned off and the entire internal control circuitry is switched off.

Power Good (PG)

The TPS62135x has a built in power good (PG) function to indicate whether the output voltage has reached its target. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an open-drain output that requires a pull-up resistor to any voltage up to a voltage level of the input voltage at VIN. It can sink 2 mA of current and maintain its specified logic low level. PG is low when the device is turned off due to EN, UVLO or thermal shutdown, so it can be used to actively discharge Vout. VIN must remain present for the PG pin to stay low.

In case VSEL is used to change the output voltage during operation, PG is not blanked for a change from low output voltage to high output voltage. It therefore will indicate "power bad" if the voltage step is large enough to trigger the power good comparator.

If the power good output is not used, it is recommended to tie to GND or leave open.

Pin-Selectable Output Voltage (VSEL and FB2)

The output voltage of the TPS62135x is set by the resistor divider from VOUT to FB to GND. The topology requires a voltage divider on FB, so the minimum output voltage is 0.8 V while the feedback voltage on the FB pin is 0.7 V.

VSEL and FB2 can optionally be used to enable a second resistor from FB2 to GND which increases the divider ratio, hence increasing the output voltage. See Typical Application using VSEL and FB2.


When MODE is set low, the device operates in PWM or PFM mode depending on the output current. Automatic Efficiency Enhancement (AEE) is enabled for highest efficiency over a wide input voltage, output voltage and output current range. The MODE pin allows to force PWM mode when set high. In forced PWM mode, AEE is disabled. See also Power Save Mode Operation (PWM/PFM).

Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the input voltage trips below the threshold for a falling supply voltage.

Thermal Shutdown

The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C (typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG goes low. When TJ decreases below the hysteresis amount of typically 20°C, the converter resumes normal operation, beginning with Soft-Start. During a PFM skip pause, the thermal shutdown is not active. See also Power Save Mode Operation (PWM/PFM).

Device Functional Modes

Pulse Width Modulation (PWM) Operation

TPS62135x has two operating modes: Forced PWM mode discussed in this section and PWM/PFM as discussed in Power Save Mode Operation (PWM/PFM).

With the MODE pin set to high, the TPS62135x operates with pulse width modulation in continuous conduction mode (CCM) with a nominal switching frequency of 2.5 MHz. The frequency variation in PWM is controlled and depends on VIN, VOUT and the inductance. The on-time in forced PWM mode is given by:

Equation 1. TPS62135 TPS621351 TONinPWM.gif

Power Save Mode Operation (PWM/PFM)

When the MODE pin is low, Power Save Mode is allowed. The device operates in PWM mode as long the output current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than half the inductor's ripple current. For improved transient response, PWM mode is forced for 8 switching cycles if the output voltage is above target due to a load release. The Power Save Mode is entered seamlessly, if the load current decreases and the MODE pin is set low. This ensures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor current is discontinuous.

In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency. The transition into and out of Power Save Mode is seamless in both directions.

The AEE function in TPS62135 and TPS621351 adjust the on-time (TON) in power save mode depending on the input voltage and the output voltage to maintain highest efficiency. The on-time, in steady-state operation, can be estimated as:

Equation 2. TPS62135 TPS621351 equation_TonAEE.gif

For very small output voltages, an absolute minimum on-time of about 50 ns is kept to limit switching losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using TON, the typical peak inductor current in Power Save Mode is approximated by:

Equation 3. TPS62135 TPS621351 equation_ILPSM.gif

There is a minimum off-time which limits the duty cycle of the TPS62135x. When VIN decreases to typically 15% above VOUT, the TPS62135x does not enter Power Save Mode, regardless of the load current. The device maintains output regulation in PWM mode.

The output voltage ripple in power save mode is given by Equation 4:

Equation 4. TPS62135 TPS621351 equation_dVPFM.gif

100% Duty-Cycle Operation

The duty cycle of the buck converter operated in PWM mode is given as D = VOUT/VIN. The duty cycle increases as the input voltage comes close to the output voltage and the off-time gets smaller. When the minimum off-time of typically 80ns is reached, TPS62135 scales down its switching frequency while it approaches 100% mode. In 100% mode it keeps the high-side switch on continuously. The high-side switch stays turned on as long as the output voltage is below the internal set point. This allows the conversion of small input to output voltage differences, for example for longest operation time of battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.

The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, can be calculated as:


Equation 5. TPS62135 TPS621351 equationVINmin.gif


IOUT is the output current,

RDS(on) is the on-state resistance of the high-side FET and

RL is the DC resistance of the inductor used.

HICCUP Current Limit And Short Circuit Protection (TPS62135 only)

The TPS62135 is protected against overload and short circuit events. If the inductor current exceeds the current limit I(LIMH), the high side switch is turned off and the low side switch is turned on to ramp down the inductor current. The high side FET turns on again only if the current in the low side FET has decreased below the low side current limit threshold. Once the high side switch current limit is triggered for 512 subsequent switching cycles, the device stops switching. After a typical delay of 800 µs, the device begins a new Soft-Start cycle. This is called HICCUP short circuit protection. TPS62135 repeats this mode until the short circuit condition disappears.

Due to internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic current limit is given as:

Equation 6. TPS62135 TPS621351 equation_Ipeaktyp2.gif


ILIMH is the static current limit as specified in the electrical characteristics

L is the effective inductance at the peak current

VL is the voltage across the inductor (VIN - VOUT) and

tPD is the internal propagation delay of typically 50 ns.

The current limit can exceed static values, especially if the input voltage is high and very small inductances are used. The dynamic high side switch peak current can be calculated as follows:

Equation 7. TPS62135 TPS621351 equation_Ipeaktyp.gif

Current Limit And Short Circuit Protection (TPS621351 only)

The TPS621351 is protected by a current limit the same as the TPS62135 but does not turn off after a certain time. This allows it to provide the maximum current, for example, charging a large output capacitance without the need to increase the Soft-Start time. Equation 6 and Equation 7 also apply.

Soft-Start / Tracking (SS/TR)

The internal Soft-Start circuitry controls the output voltage slope during startup. This avoids excessive inrush current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a delay of about 200 μs then the internal reference and hence VOUT rises with a slope controlled by an external capacitor connected to the SS/TR pin.

Leaving SS/TR pin un-connected provides fastest startup behavior with 150 µs typically.

If the device is set to shutdown (EN = GND), undervoltage lockout or thermal shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low level. Returning from those states causes a new startup sequence as set by the SS/TR connection.

A voltage supplied to SS/TR can be used to track a master voltage. The output voltage follows this voltage in both directions up and down in forced PWM mode. In PFM mode, the output voltage decreases based on the load current. The SS/TR pin of several devices must not be connected with each other.

Output Discharge Function (TPS62135 only)

The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is being disabled but also to keep the output voltage close to 0 V when the device is off. The output discharge feature is only active once TPS62135 has been enabled at least once since the supply voltage was applied. The internal discharge resistor is connected to the VOS pin. The discharge function is enabled as soon as the device is disabled, in thermal shutdown or in undervoltage lockout. The minimum supply voltage required for the discharge function to remain active typically is 2 V. Output discharge is not activated during a HICCUP current limit event.

Starting into a Pre-Biased Load (TPS621351 only)

The TPS621351 is capable of starting into a pre-biased output. The device only starts switching when the internal Soft-Start ramp is equal or higher than the feedback voltage. If the voltage at the feedback pin is biased to a higher voltage than the nominal value, the TPS621351 does not start switching unless the voltage at the feedback pin drops to the target.

This functionality actually also applies to TPS62135 but the discharge function in TPS62135 keeps the voltage close to 0 V, so starting into a pre-biased output does not apply.