The TPS6242x includes two synchronous step-down converters. The converters operate with typically 2.25-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. If power-save mode is enabled, the converters automatically enter power-save mode at light load currents and operate in pulse frequency modulation (PFM). During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on. If the current in the N-channel MOSFET is above the N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit. The two DC/DC converters operate synchronized to each other. A 180° phase shift between converter 1 and converter 2 decreases the input RMS current.
In the adjustable output voltage version TPS62420 the converter 1 output voltage can be set through an external resistor network on pin DEF_1, which operates as an analog input. In this case, the output voltage can be set in the range of 0.6 V to VIN. The FB1 pin must be directly connected to the converter 1 output voltage VOUT1. It feeds back the output voltage directly to the regulation loop.
The output voltage of converter 1 can also be changed by the EasyScale™ serial interface. This makes the device very flexible for output voltage adjustment. In this case, the device uses an internal resistor network.
In the fixed default output voltage version like TPS62421, the DEF_1 pin is configured as a digital input. The converter 1 defaults to 1.2 V or 1.8 V depending on the level of DEF_1 pin. If DEF_1 is low the default is 1.2 V; if high, the default is 1.8 V. With the EasyScale™ interface, the output voltage for each DEF_1 pin condition (high or low) can be changed.
In the adjustable output voltage version TPS62420, the converter 2 output voltage is set by an external resistor divider connected to ADJ2 pin and uses an external feed-forward capacitor of 33 pF.
In fixed output voltage version TPS62421, the default output voltage is fixed to 1.8 V. In this case, the ADJ2 pin must be connected directly to the converter 2 output voltage VOUT2. It is also possible to change the output voltage of converter 2 through the EasyScale™ interface. In this case, the ADJ2 pin must be directly connected to converter 2 output voltage VOUT2 and no external resistors may be connected.
This feature reduces the voltage undershoots and overshoots at load steps from light to heavy load and vice versa. It is activated in power-save mode operation. It provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. This improves load transient behavior.
At light loads, in which the converter operate in PFM mode, the output voltage is regulated typically 1% higher than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it reaches the skip comparator low threshold set to –2% below the nominal value and enters PWM mode. During a load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel switch.
The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery and disables the converters. The under-voltage lockout threshold is typically 1.5 V, maximum is 2.35 V. In case the default register values are overwritten by the interface, the new values in the registers REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage does not fall under the undervoltage lockout threshold, independent of whether the converters are disabled.
The MODE/DATA pin allows mode selection between forced PWM mode and power-save mode for both converters. Furthermore, this pin is a multi-purpose pin and provides (besides mode selection) a one-pin interface to receive serial data from a host to set the output voltage. This is described in the section EasyScale™ interface.
Connecting this pin to GND enables the automatic PWM and power-save mode operation. The converters operate in fixed-frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, maintaining high efficiency over a wide load current range.
Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode even at light load currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power-save mode during light loads. For additional flexibility it is possible to switch from power-save mode to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements.
In case the operation mode will be changed from forced PWM mode (MODE/DATA = High) to power-save mode Enable (MODE/DATA = 0) the power-save mode will be enabled after a delay time of typically ttimeout, which is a maximum of 520 μs.
The forced PWM mode operation is enabled immediately with pin MODE/DATA set to 1.
The device has for each converter a separate EN pin to start up each converter independently. If EN1 and EN2 are set to high, the corresponding converter starts up with soft-start.
Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically 1.2 μA. In this mode, the P- and N-channel MOSFETs are turned-off and the entire internal control circuitry is switched off. For proper operation the EN1 and EN2 pins must be terminated and must not be left floating.
The DEF_1 pin is dedicated to converter 1 and makes the output voltage selection very flexible to support dynamic voltage management. Depending on the device version, this pin works either as:
1. Analog input for adjustable output voltage setting (TPS62420): Connecting an external resistor network to this pin adjusts the default output voltage to any value starting from 0.6 V to VIN.
2. Digital input for fixed default output voltage selection (TPS62421): In case this pin is tied to low level, the output voltage is set according to the value in register REG_DEF_1_Low. The default voltage will be 1.2 V. If tied to high level, the output voltage is set according to the value in register REG_DEF_1_High. The default value in this case is 1.8 V. Depending on the level of pin DEF_1, it selects between the two registers REG_DEF_1_Low and REG_DEF_1_High for output voltage setting. Each register content (and therefore output voltage) can be changed individually through the EasyScale™ interface. This makes the device very flexible in terms of output voltage setting; see Table 4.
In PWM mode the converters operate with a 180° turnon phase shift of the PMOS (high side) transistors. It prevents the high-side switches of both converters to be turned on simultaneously, and therefore smooths the input current. This feature reduces the surge current drawn from the supply.
As soon as the junction temperature, TJ, exceeds typically 150°C the device goes into thermal shutdown. In this mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis again.
Both outputs are short circuit protected with maximum output current = ILIMF (P-MOS and N-MOS). Once the PMOS switch reaches its current limit, it will be turned off and the NMOS turned on. The PMOS only turns on again, once the current in the NMOS decreases below the NMOS current limit.
The two converters have an internal soft-start circuit that limits the inrush current during start-up. During soft-start, the output voltage ramp up is controlled as shown in Figure 7.
The converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range; that is, the minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as:
With decreasing load current, the device automatically switches into pulse-skipping operation in which the power stage operates intermittently based on load demand. By running cycles periodically the switching losses are minimized and the device runs with a minimum quiescent current maintaining high efficiency.
The power-save mode is enabled with MODE/DATA pin set to 0 for both converters. If the load current of a converter decreases, this converter will enter power-save mode operation automatically. The transition to power-save mode of a converter is independent from the operating condition of the other converter. During power-save mode the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The converter will position the output voltage in PFM mode to typically 1.01 × VOUT. This voltage positioning feature minimizes voltage drops caused by a sudden load step.
To optimize the converter efficiency at light load the average inductor current is monitored. The device changes from PWM mode to power-save mode, if in PWM mode the inductor current falls below a certain threshold. The typical output current threshold depends on VIN and can be calculated according to Equation 2 for each converter.
Equation 2: Average output current threshold to enter PFM mode
Equation 3: Average output current threshold to leave PFM mode
To keep the output voltage ripple in power-save mode low, the output voltage is monitored with a single threshold comparator (skip comparator). As the output voltage falls below the skip comparator threshold (skip comp) of 1.01 × VOUTnominal, the corresponding converter starts switching for a minimum time period of typically 1 μs and provides current to the load and the output capacitor. Therefore the output voltage increases and the device maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this moment all switching activity is stopped and the quiescent current is reduced to minimum. The load is supplied by the output capacitor until the output voltage has dropped below the threshold again. Hereupon the device starts switching again. The power-save mode is exited and PWM mode entered in case the output current exceeds the current IOUT_PFM_leave, or if the output voltage falls below a second comparator threshold, called skip comparator low (skip comp Low) threshold. This skip comparator low threshold is set to –2% below nominal Vout, and enables a fast transition from power-save mode to PWM mode during a load step. In power-save mode the quiescent current is reduced typically to 19 μA for one converter and 32 μA for both converters active. This single skip comparator threshold method in power-save mode results in a very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing output capacitor values minimizes the output ripple. The power-save mode can be disabled through the MODE/DATA pin set to high. Both converters then operate in fixed PWM mode. Power-save mode enable/disable applies to both converters.
The EasyScale™ interface is a simple but very flexible one-pin interface to configure the output voltage of both DC–DC converters. The interface is based on a master-slave structure, where the master is typically a micro-controller or application processor. Figure 8 and Table 1 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte. The device specific address byte is fixed to 4E hex. The data byte consists of five bit for information, two address bits and the RFA bit. RFA bit set to high indicates the Request For Acknowledge condition, but the acknowledge condition is only applied if the protocol was received correctly.
The advantage of EasyScale™ interface compared to other one-pin interfaces is that its bit detection is, to a large extent, independent from the bit transmission rate. It can automatically detect bit rates from 1.7 kbps to 160 kbps. Furthermore, the interface is shared with the MODE/DATA pin and requires therefore no additional pin.
Prior to both bytes, device address byte and data byte, a start condition needs to be applied. For this, the MODE/DATA pin needs to be pulled high for at least tStart before the bit transmission starts with the falling edge. In case the MODE/DATA line was already at high level (forced PWM mode selection) no start condition need be applied prior the device address byte.
The transmission of each byte needs to be closed with an end-of-stream condition for at least TEOS.
The bit detection is based on a PWM scheme, where the criterion is the relation between tLOW and tHIGH. It can be simplified to:
High Bit: tHigh > tLow, but with tHigh at least 2 x tLow, see Figure 11
Low Bit: tLow > tHigh, but with tLow at least 2 x tHigh, see Figure 11
The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge. Depending on the relation between tLow and tHigh a 0 or 1 is detected.
The acknowledge condition is only applied if:
In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time tACKN, which is maximum. 520 μs. The acknowledge condition is valid after an internal delay time tvalACK. This means the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master controller keeps the line low during this time.
The master device can detect the acknowledge condition with its input by releasing the MODE/DATA pin after tvalACK and read back a 0.
In case of an invalid device address or not correctly received protocol, no acknowledge condition will be applied, thus the internal MOSFET will not be turned on and the external pullup resistor pulls MODE/DATA pin high after tvalACK. The MODE/DATA pin can be used again after the acknowledge condition ends.
The acknowledge condition may only be requested in case the master device has an open-drain output.
In case of a push-pull output stage TI recommends to use a series resistor in the MODE/DATA line to limit the current to 500 μA in case of an accidentally requested acknowledge to protect the internal ACKN-MOSFET.
Because of the MODE/DATA pin is used for two functions, interface and a mode selection, the device needs to determine when it has to decode the bit stream or to change the operation mode.
The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level. The device stays also in forced PWM mode during the whole time of a protocol reception.
With a falling edge on the MODE/DATA pin the device starts bit decoding. If the MODE/DATA pin stays low for at least ttimeout, the device gets an internal time-out and power-save mode operation is enabled.
A protocol which is sent within this time will be ignored, because the falling edge for the mode change will be first interpreted as start of the first bit. In this case, TI recommends to send first the protocol and change at the end of the protocol to power-save mode.
|BYTE||BIT NUMBER||NAME||TRANSMISSION DIRECTION||DESCRIPTION|
|Device Address Byte||7||DA7||IN||0 MSB device address|
|0||DA0||IN||0 LSB device address|
|Data Byte||7 (MSB)||RFA||IN||Request for acknowledge, if high, acknowledge condition will applied by the device|
|6||A1||Address bit 1|
|5||A0||Address bit 0|
|4||D4||Data bit 4|
|3||D3||Data bit 3|
|2||D2||Data bit 2|
|1||D1||Data bit 1|
|0 (LSB)||D0||Data bit 0|
|ACK||OUT||Acknowledge condition active 0, this condition will only be applied in case RFA bit is set. Open-drain output, line needs to be pulled high by the host with a pullup resistor.|
|This feature can only be used if the master has an open-drain output stage. In case of a push-pull output stage acknowledge condition may not be requested!|
Three registers with a data content of 5 bits can be addressed. With 5 bit data content, 32 different values for each register are available. Table 2 shows the addressable registers to set the output voltage when DEF_1 pin works as digital input. In this case, converter 1 has a related register for each DEF_1 pin condition, and one register for converter 2. With a high or low condition on pin DEF_1 (TPS62421) either the content of register REG_DEF_1_High/REG_DEF1_Low is selected. The output voltage of converter 1 is set according to the values in Table 4. Table 3 shows the addressable registers if DEF_1 pin acts as analog input with external resistors connected. In this case one register is available for each converter. The output voltage of converter 1 is set according to the values in Table 5. For converter 2, the available voltages are shown in Table 6. To generate these output voltages a precise internal resistor divider network is used, making external resistors unnecessary (less board space), and provides higher output voltage accuracy. The Interface is activated if at least one of the converters is enabled (EN1 or EN2 is high). After the start-up time tStart (170 μs) the interface is ready for data reception.
|TPS62421||REG_DEF_1_High||Converter 1 output voltage setting for DEF_1 = High condition. The content of the register is active with DEF1_ Pin high.||high||0||1||Output voltage setting, see Table 4|
|REG_DEF_1_Low||Converter 1 output voltage setting||low||0||0||Output voltage setting, see Table 4|
|REG_DEF_2||Converter 2 output voltage||n/a||1||0||Output voltage setting, see Table 6|
|Do not use||1||1|
|REG_DEF_1_High||Not available in TPS62420 adjustable version||0||1|
|REG_DEF_1_Low||Converter 1 output voltage setting||0||0||TPS62420 see Table 5|
|REG_DEF_2||Converter 2 output voltage||1||0||TPS62420 see Table 6, connect ADJ2 pin directly to VOUT2|
|Do not use||1||1|
|30||1.55||1.8 (default TPS62421)||1||1||1||1||0|
| TPS62420 OUTPUT VOLTAGE [V]
|0||VOUT1 Adjustable Output with Resistor Network on DEF_1 Pin||0||0||0||0||0|
|0.6 V with DEF_1 pin connected to VOUT1|
| OUTPUT VOLTAGE [V]
FOR REGISTER REG_DEF_2
|0||VOUT2 Adjustable Output with Resistor Network on ADJ2 (TPS62420)||0||0||0||0||0|
|0.6 V with ADJ2 pin connected to VOUT2 (TPS62420)|
|18||1.8 (default TPS62421)||1||0||0||1||0|