SLVSFU1B April   2023  – October 2023 TPS62874-Q1 , TPS62875-Q1 , TPS62876-Q1 , TPS62877-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6.   Device Options
  7. 5 Pin Configuration and Functions
  8. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - Q100
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  9. 7 Parameter Measurement Information
  10. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency DCS-Control Topology
      2. 8.3.2  Forced-PWM and Power-Save Modes
      3. 8.3.3  Transient Non-Synchronous Mode (optional)
      4. 8.3.4  Precise Enable
      5. 8.3.5  Start-Up
      6. 8.3.6  Switching Frequency Selection
      7. 8.3.7  Output Voltage Setting
        1. 8.3.7.1 Output Voltage Range
        2. 8.3.7.2 Output Voltage Setpoint
        3. 8.3.7.3 Non-Default Output Voltage Setpoint
        4. 8.3.7.4 Dynamic Voltage Scaling
        5. 8.3.7.5 Droop Compensation
      8. 8.3.8  Compensation (COMP)
      9. 8.3.9  Mode Selection / Clock Synchronization (MODE/SYNC)
      10. 8.3.10 Spread Spectrum Clocking (SSC)
      11. 8.3.11 Output Discharge
      12. 8.3.12 Undervoltage Lockout (UVLO)
      13. 8.3.13 Overvoltage Lockout (OVLO)
      14. 8.3.14 Overcurrent Protection
        1. 8.3.14.1 Cycle-by-Cycle Current Limiting
        2. 8.3.14.2 Hiccup Mode
        3. 8.3.14.3 Current-Limit Mode
      15. 8.3.15 Power Good (PG)
        1. 8.3.15.1 Standalone / Primary Device Behavior
        2. 8.3.15.2 Secondary Device Behavior
      16. 8.3.16 Remote Sense
      17. 8.3.17 Thermal Warning and Shutdown
      18. 8.3.18 Stacked Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Undervoltage Lockout
      3. 8.4.3 Standby
      4. 8.4.4 On
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 8.5.3 HS-Mode Protocol
      4. 8.5.4 I2C Update Sequence
      5. 8.5.5 I2C Register Reset
      6. 8.5.6 Dynamic Voltage Scaling (DVS)
    6. 8.6 Device Registers
  11. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Selecting the Input Capacitors
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor CC
        6. 9.2.2.6 Selecting the Compensation Capacitor CC2
      3. 9.2.3 Application Curves
    3. 9.3 Application Using Two TPS62876-Q1 in a Stacked Configuration
      1. 9.3.1 Design Requirements For Two Stacked Devices
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Selecting the Compensation Resistor
        2. 9.3.2.2 Selecting the Output Capacitors
        3. 9.3.2.3 Selecting the Compensation Capacitor CC
      3. 9.3.3 Application Curves for Two Stacked Devices
    4. 9.4 Application Using Three TPS62876-Q1 in a Stacked Configuration
      1. 9.4.1 Design Requirements For Three Stacked Devices
      2. 9.4.2 Detailed Design Procedure
        1. 9.4.2.1 Selecting the Compensation Resistor
        2. 9.4.2.2 Selecting the Output Capacitors
        3. 9.4.2.3 Selecting the Compensation Capacitor CC
      3. 9.4.3 Application Curves for Three Stacked Devices
    5. 9.5 Best Design Practices
    6. 9.6 Power Supply Recommendations
    7. 9.7 Layout
      1. 9.7.1 Layout Guidelines
      2. 9.7.2 Layout Example
  12. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  13. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.5 Start-Up

When the voltage on the VIN pin exceeds the positive-going UVLO threshold, the device initializes as follows:

  • The device pulls the EN pin low.
  • The device enables the internal reference voltage.
  • The device reads the state of the VSEL, FSEL and SYNC_OUT pins.
  • The device loads the default values into the device registers.

When initialization is complete, the device enables I2C communication and releases the EN pin. The external circuitry controlling the EN pin now determines the behavior of the device:

  • If the EN pin is low, the device is disabled: write to and read from the device registers, but the DC/DC converter does not operate.
  • If the EN pin is high, the device is enabled: write to and read from the device registers and, after a short delay from EN pin going high, the DC/DC converter starts to ramp up its output.

Figure 8-7 shows the start-up sequence when the EN pin is pulled up to VIN.


GUID-117EF73B-47DD-40BA-87E5-67E6EAF50C4D-low.svg
Figure 8-7 Start-Up Timing When EN is Pulled Up to VIN

Figure 8-8 shows the start-up sequence when an external signal is connected to the EN pin.


GUID-E05B2501-44D8-4FE4-BA3F-8669298FA884-low.svg
Figure 8-8 Start-Up Timing When an External Signal is Connected to the EN Pin

The SSTIME[1:0] bits in the CONTROL2 register select the duration of the soft-start ramp:

  • td(RAMP) = 500 μs
  • td(RAMP) = 770 μs
  • td(RAMP) = 1 ms (default)
  • td(RAMP) = 2 ms

If you program new output voltage setpoint (VOUT[7:0]), output voltage range (VRANGE[1:0]), or soft-start time (SSTIME[1:0]) settings when the device has already begun its soft-start sequence, the device ignores the new values until the soft-start sequence is complete. For example, if you change the value of VSET[7:0] during soft-start, the device first ramps to the value that VSET[7:0] had when the soft-start sequence began and then, when soft-start is complete, ramps up or down to the new value.

The device can start up into a prebiased output. In this case, only a portion of the internal voltage ramp is seen externally (see Figure 8-9).


GUID-CDDACB62-AE9E-4EB8-95BD-0F79ACA9E4CD-low.svg
Figure 8-9 Start-Up into a Prebiased Output

Note that the device always operates in DCM/PFM allowed during the start-up ramp, regardless of other configuration settings or operating conditions.