SWCS138E June   2017  – December 2022 TPS650864

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Total Current Consumption
    6. 7.6  Electrical Characteristics: Reference and Monitoring System
    7. 7.7  Electrical Characteristics: Buck Controllers
    8. 7.8  Electrical Characteristics: Synchronous Buck Converters
    9. 7.9  Electrical Characteristics: LDOs
    10. 7.10 Electrical Characteristics: Load Switches
    11. 7.11 Digital Signals: I2C Interface
    12. 7.12 Digital Input Signals (CTLx)
    13. 7.13 Digital Output Signals (IRQB, GPOx)
    14. 7.14 Timing Requirements
    15. 7.15 Switching Characteristics
    16. 7.16 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  TPS6508640 Design and Settings
      1. 8.3.1 TPS6508640 OTP Summary
    4. 8.4  TPS65086401 Design and Settings
      1. 8.4.1 TPS65086401 OTP Summary
      2.      31
    5. 8.5  TPS6508641 Design and Settings
      1. 8.5.1 TPS6508641 OTP Summary
    6. 8.6  TPS65086470 Design and Settings
      1. 8.6.1 TPS65086470 OTP Summary
    7. 8.7  SMPS Voltage Regulators
      1. 8.7.1 Controller Overview
      2. 8.7.2 Converter Overview
      3. 8.7.3 DVS
      4. 8.7.4 Decay
      5. 8.7.5 Current Limit
    8. 8.8  LDOs and Load Switches
      1. 8.8.1 VTT LDO
      2. 8.8.2 LDOA1–LDOA3
      3. 8.8.3 Load Switches
    9. 8.9  Power Goods (PGOOD or PG) and GPOs
    10. 8.10 Power Sequencing and VR Control
      1. 8.10.1 CTLx Sequencing
      2. 8.10.2 PG Sequencing
      3. 8.10.3 Enable Delay
      4. 8.10.4 Power-Up Sequence
      5. 8.10.5 Power-Down Sequence
      6. 8.10.6 Sleep State Entry and Exit
      7. 8.10.7 Emergency Shutdown
    11. 8.11 Device Functional Modes
      1. 8.11.1 Off Mode
      2. 8.11.2 Standby Mode
      3. 8.11.3 Active Mode
    12. 8.12 I2C Interface
      1. 8.12.1 F/S-Mode Protocol
    13. 8.13 Register Maps
      1. 8.13.1  Register Map Summary
      2. 8.13.2  DEVICEID1: 1st PMIC Device and Revision ID Register (offset = 00h) [reset = X]
      3. 8.13.3  DEVICEID2: 2nd PMIC Device and Revision ID Register (offset = 01h) [reset = X]
      4. 8.13.4  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
      5. 8.13.5  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
      6. 8.13.6  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
      7. 8.13.7  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 05h) [reset = 0000 0000]
      8. 8.13.8  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = X]
      9. 8.13.9  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = X]
      10. 8.13.10 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = X]
      11. 8.13.11 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = X]
      12. 8.13.12 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = X]
      13. 8.13.13 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = X]
      14. 8.13.14 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = X]
      15. 8.13.15 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = X]
      16. 8.13.16 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = X]
      17. 8.13.17 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = X]
      18. 8.13.18 DISCHCTRL1: 1st Discharge Control Register (offset = 40h) [reset = X]
      19. 8.13.19 DISCHCTRL2: 2nd Discharge Control Register (offset = 41h) [reset = X]
      20. 8.13.20 DISCHCTRL3: 3rd Discharge Control Register (offset = 42h) [reset = X]
      21. 8.13.21 PG_DELAY1: 1st Power Good Delay Register (offset = 43h) [reset = X]
      22. 8.13.22 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      23. 8.13.23 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = X]
      24. 8.13.24 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = X]
      25. 8.13.25 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = X]
      26. 8.13.26 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = X]
      27. 8.13.27 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = X]
      28. 8.13.28 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = X]
      29. 8.13.29 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = X]
      30. 8.13.30 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = X]
      31. 8.13.31 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = X]
      32. 8.13.32 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = X]
      33. 8.13.33 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = X]
      34. 8.13.34 PG_DELAY2: 2nd Power Good Delay Register (offset = 9Dh) [reset = X]
      35. 8.13.35 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = X]
      36. 8.13.36 I2C_RAIL_EN1: 1st VR Pin Enable Override Register (offset = A0h) [reset = X]
      37. 8.13.37 I2C_RAIL_EN2/GPOCTRL: 2nd VR Pin Enable Override and GPO Control Register (offset = A1h) [reset = X]
      38. 8.13.38 PWR_FAULT_MASK1: 1st VR Power Fault Mask Register (offset = A2h) [reset = X]
      39. 8.13.39 PWR_FAULT_MASK2: 2nd VR Power Fault Mask Register (offset = A3h) [reset = X]
      40. 8.13.40 GPO1PG_CTRL1: 1st GPO1 PG Control Register (offset = A4h) [reset = X]
      41. 8.13.41 GPO1PG_CTRL2: 2nd GPO1 PG Control Register (offset = A5h) [reset = X]
      42. 8.13.42 GPO4PG_CTRL1: 1st GPO4 PG Control Register (offset = A6h) [reset = X]
      43. 8.13.43 GPO4PG_CTRL2: 2nd GPO4 PG Control Register (offset = A7h) [reset = X]
      44. 8.13.44 GPO2PG_CTRL1: 1st GPO2 PG Control Register (offset = A8h) [reset = X]
      45. 8.13.45 GPO2PG_CTRL2: 2nd GPO2 PG Control Register (offset = A9h) [reset = X]
      46. 8.13.46 GPO3PG_CTRL1: 1st GPO3 PG Control Register (offset = AAh) [reset = X]
      47. 8.13.47 GPO3PG_CTRL2: 2nd GPO3 PG Control Register (offset = ABh) [reset = X]
      48. 8.13.48 MISCSYSPG Register (offset = ACh) [reset = X]
        1. 8.13.48.1 VTT_DISCH_CTRL Register (offset = ADh) [reset = X]
      49. 8.13.49 LDOA1_SWB2_CTRL: LDOA1 and SWB2 Control Register (offset = AEh) [reset = X]
      50. 8.13.50 PG_STATUS1: 1st Power Good Status Register (offset = B0h) [reset = 0000 0000]
      51. 8.13.51 PG_STATUS2: 2nd Power Good Status Register (offset = B1h) [reset = 0000 0000]
      52. 8.13.52 PWR_FAULT_STATUS1: 1st Power Fault Status Register (offset = B2h) [reset = 0000 0000]
      53. 8.13.53 PWR_FAULT_STATUS2: 2nd Power Fault Status Register (offset = B3h) [reset = 0000 0000]
      54. 8.13.54 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]
      55. 8.13.55 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
      56. 8.13.56 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]
  9. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Controller Design Procedure
          1. 9.2.2.1.1 Selecting the Inductor
          2. 9.2.2.1.2 Selecting the Output Capacitors
          3. 9.2.2.1.3 Selecting the FETs
          4. 9.2.2.1.4 Bootstrap Capacitor
          5. 9.2.2.1.5 Setting the Current Limit
          6. 9.2.2.1.6 Selecting the Input Capacitors
        2. 9.2.2.2 Converter Design Procedure
          1. 9.2.2.2.1 Selecting the Inductor
          2. 9.2.2.2.2 Selecting the Output Capacitors
          3. 9.2.2.2.3 Selecting the Input Capacitors
        3. 9.2.2.3 LDO Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Layout
        1. 9.2.4.1 Layout Guidelines
        2. 9.2.4.2 Layout Example
      5. 9.2.5 VIN 5-V Application
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Design Procedure
        3. 9.2.5.3 Application Curves
    3. 9.3 Power Supply Coupling and Bulk Capacitors
    4. 9.4 Do's and Don'ts
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.7 SMPS Voltage Regulators

The buck controllers integrate gate drivers for external power stages with programmable current limit (set by an external resistor at ILIMx pin), which allows for optimal selection of external passive components based on the desired system load. The buck converters include integrated power stage and require a minimum number of pins for power input, inductor, and output voltage feedback input. Combined with high-frequency switching, all these features allow use of inductors in small form factor, thus reducing total-system cost and size.

BUCK1–BUCK6 have selectable auto- and forced-pulse width modulation (PWM) mode through the BUCKx_MODE bit in the BUCKxCTRL register. In default auto mode, the VR automatically switches between PWM and pulsed frequency modulation (PFM) depending on the output load to maximize efficiency.

All controllers and converters can be used with the default VOUT or can have their voltage dynamically changed at any time. This means that the rails can be default programmed for any available VOUT by OTP programming at the factory, so the device starts up with the default voltage, or during operation the rail can be configured by I2C to another operating VOUT while the rail is enable or disabled. There are two step sizes or ranges available for VOUT selection : 10-mV and 25-mV steps. The step-size range must be selected prior to use and must be programmed in the OTP at the factory. It is not subject to change during operation.

For the 10-mV step-size range VOUT options, see Table 8-22. For the 25-mV step-size range VOUT options, see Table 8-23.

Table 8-22 10-mV Step-Size VOUT Range
VID BITSVOUTVID BITSVOUTVID BITSVOUT
0000000001010110.8310101101.26
00000010.4101011000.8410101111.27
00000100.4201011010.8510110001.28
00000110.4301011100.8610110011.29
00001000.4401011110.8710110101.30
00001010.4501100000.8810110111.31
00001100.4601100010.8910111001.32
00001110.4701100100.9010111011.33
00010000.4801100110.9110111101.34
00010010.4901101000.9210111111.35
00010100.5001101010.9311000001.36
00010110.5101101100.9411000011.37
00011000.5201101110.9511000101.38
00011010.5301110000.9611000111.39
00011100.5401110010.9711001001.40
00011110.5501110100.9811001011.41
00100000.5601110110.9911001101.42
00100010.5701111001.0011001111.43
00100100.5801111011.0111010001.44
00100110.5901111101.0211010011.45
00101000.6001111111.0311010101.46
00101010.6110000001.0411010111.47
00101100.6210000011.0511011001.48
00101110.6310000101.0611011011.49
00110000.6410000111.0711011101.50
00110010.6510001001.0811011111.51
00110100.6610001011.0911100001.52
00110110.6710001101.1011100011.53
00111000.6810001111.1111100101.54
00111010.6910010001.1211100111.55
00111100.7010010011.1311101001.56
00111110.7110010101.1411101011.57
01000000.7210010111.1511101101.58
01000010.7310011001.1611101111.59
01000100.7410011011.1711110001.60
01000110.7510011101.1811110011.61
01001000.7610011111.1911110101.62
01001010.7710100001.2011110111.63
01001100.7810100011.2111111001.64
01001110.7910100101.2211111011.65
01010000.8010100111.2311111101.66
01010010.8110101001.2411111111.67
01010100.8210101011.25
Table 8-23 25-mV Step-Size VOUT Range
VID BITSVOUT (Converters)VOUT (Controllers)VID BITSVOUTVID BITSVOUT
00000000001010111.47510101102.550
00000010.4251.00001011001.50010101112.575
00000100.4501.00001011011.52510110002.600
00000110.4751.00001011101.55010110012.625
00001000.5001.00001011111.57510110102.650
00001010.5251.00001100001.60010110112.675
00001100.5501.00001100011.62510111002.700
00001110.5751.00001100101.65010111012.725
00010000.6001.00001100111.67510111102.750
00010010.6251.00001101001.70010111112.775
00010100.6501.00001101011.72511000002.800
00010110.6751.00001101101.75011000012.825
00011000.7001.00001101111.77511000102.850
00011010.7251.00001110001.80011000112.875
00011100.7501.00001110011.82511001002.900
00011110.7751.00001110101.85011001012.925
00100000.8001.00001110111.87511001102.950
00100010.8251.00001111001.90011001112.975
00100100.8501.00001111011.92511010003.000
00100110.8751.00001111101.95011010013.025
00101000.9001.00001111111.97511010103.050
00101010.9251.00010000002.00011010113.075
00101100.9501.00010000012.02511011003.100
00101110.9751.00010000102.05011011013.125
00110001.0001.00010000112.07511011103.150
00110011.0251.02510001002.10011011113.175
00110101.0501.05010001012.12511100003.200
00110111.0751.07510001102.15011100013.225
00111001.1001.10010001112.17511100103.250
00111011.1251.12510010002.20011100113.275
00111101.1501.15010010012.22511101003.300
00111111.1751.17510010102.25011101013.325
01000001.2001.20010010112.27511101103.350
01000011.2251.22510011002.30011101113.375
01000101.2501.25010011012.32511110003.400
01000111.2751.27510011102.35011110013.425
01001001.3001.30010011112.37511110103.450
01001011.3251.32510100002.40011110113.475
01001101.3501.35010100012.42511111003.500
01001111.3751.37510100102.45011111013.525
01010001.4001.40010100112.47511111103.550
01010011.4251.42510101002.50011111113.575
01010101.4501.45010101012.525