Product details


Regulated outputs (#) 12, 13 Vin (Min) (V) 5.6 Vin (Max) (V) 21 Iout (Max) (A) 25 Step-down DC/DC controller 3 Step-down DC/DC converter 3 Step-up DC/DC controller 0 Step-up DC/DC converter 0 LDO 4 Iq (Typ) (mA) 0.3 Features Comm Control, Dynamic Voltage Scaling, Enable, Enable Pin, I2C Control, Over Current Protection, Power Good, Power Sequencing, Synchronous Rectification, Thermal Shutdown, UVLO Fixed Operating temperature range (C) -40 to 85 Rating Catalog Processor name Zynq UltraScale+, Artix-7 Processor supplier Xilinx Shutdown current (ISD) (Typ) (uA) 65 Configurability Factory programmable, Software configurable open-in-new Find other Multi-channel ICs (PMIC)

Package | Pins | Size

VQFN (RSK) 64 64 mm² 8 x 8 open-in-new Find other Multi-channel ICs (PMIC)


  • Wide VIN Range from 5.6 V to 21 V
  • Three Variable-Output Voltage Synchronous Step-Down Controllers with D-CAP2™ Topology
    • Scalable Output Current Using External FETs With Selectable Current Limit
    • I2C DVS Control From 0.41 V to 1.67 V in 10-mV Steps or 1 V to 3.575 V in 25-mV Steps
  • Three Variable-Output Voltage Synchronous Step-Down Converters With DCS-Control Topology
    • VIN Range From 3 V to 5.5 V
    • Up to 3 A of Output Current
    • I2C DVS Control From 0.41 V to 1.67 V in 10-mV Steps or 0.425 V to 3.575 V in 25-mV Steps
  • Three LDO Regulators With Adjustable Output Voltage
    • LDOA1: I2C-Selectable Voltage From 1.35 V to 3.3 V for up to 200 mA of Output Current
    • LDOA2 and LDOA3: I2C-Selectable Voltage From 0.7 V to 1.5 V for up to 600 mA of Output Current Each
  • VTT LDO for DDR Memory Termination
  • Three Load Switches With Slew Rate Control
    • Up to 300 mA of Output Current With Voltage Drop Less Than 1.5% of Nominal Input Voltage
    • RDSON < 96 mΩ at Input Voltage of 1.8 V
  • 5-V Fixed-Output Voltage LDO (LDO5)
    • Power Supply for Gate Drivers of SMPS and for LDOA1
    • Automatic Switch to External 5-V Buck for Higher Efficiency
  • Built-in Flexibility and Configurability by Factory OTP Programming
    • Six GPI Pins Configurable to Enable (CTL1 to CTL6) or Sleep Mode Entry (CTL3 and CTL6) of Any Selected Rails
    • Four GPO Pins Configurable to Power Good of Any Selected Rails
    • Open-Drain Interrupt Output Pin
  • I2C Interface Supports Standard Mode (100 kHz), Fast Mode (400 kHz), and Fast Mode Plus (1 MHz)
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The TPS650864 device family is a single-chip power-management IC (PMIC) designed for Xilinx Zynq multiprocessor system-on-chip (MPSoCs) and field programmable gate array (FPGA) families. The TPS650864 offers an input range of 5.6 V to 21 V, enabling a wide range of applications (see the Device Comparison Table). The device is targeted for wall-powered applications or 2S, 3S, or 4S Li-Ion battery packs (NVDC or non-NVDC power architectures). See the Typical Application section for 5-V input supplies. The D-CAP2 and DCS-Control high-frequency voltage regulators use small passives to achieve a small solution size. The D-CAP2 and DCS-Control topologies have excellent transient response performance, ideal for processor core and system memory rails that have fast load switching. An I2C interface allows simple control either by an embedded controller (EC) or by an SoC. The PMIC comes in an 8-mm × 8-mm, single-row VQFN package with thermal pad for good thermal dissipation.

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Technical documentation

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Type Title Date
* Data sheet TPS650864 Configurable Multirail PMU for Xilinx® MPSoCs and FPGAs datasheet (Rev. D) Jun. 11, 2020
Technical article What’s not in the power MOSFET data sheet part 2: voltage-dependent leakage currents Jul. 23, 2021
Application note Push-Button Circuit (Rev. B) Nov. 01, 2017
Application note TPS65086x Schematic and Layout Checklist (Rev. A) Dec. 02, 2015
White paper Power management integrated buck controllers for distant point-of-load apps Aug. 14, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

TPS650860 Evaluation Module
document-generic User guide

Evaluation Module (EVM) for the TPS65086x family. The EVM provides a platform for engineers to evaluate, test, and explore the TPS650860 in a real world application use. All of the sequencing and functionality required for the processor and system is demonstrated on this board. This EVM also (...)

  • DVS
  • Sequencing
  • I2C Communication and Controls
  • Holistic System Example Architecture
  • This circuit design is tested and orderable and includes GUI and User's Guide

Design tools & simulation

SWCM008.ZIP (0 KB) - Thermal Model

Reference designs

Power reference design for Xilinx® Zynq® UltraScale+™ MPSoC applications
TIDA-01393 This reference design is a configurable power solution designed to handle the entire Xilinx® Zynq® UltraScale+ (ZU+) family of MPSoC devices across various use cases.

The various versions of the TPS65086x PMIC allow this design to power devices from the basic ZU2CG device with a dual-core Arm® (...)

document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN (RSK) 64 View options

Ordering & quality

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