SLVSCJ1B September   2014  – January 2017 TPS68470

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements - Data Transmission
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-Up Sequence and Modes
      2. 8.3.2  Clock Generation
        1. 8.3.2.1 Crystal Oscillator
        2. 8.3.2.2 Phase Locked Loop (PLL)
        3. 8.3.2.3 Spread Spectrum Modulator
        4. 8.3.2.4 Clock Drivers
      3. 8.3.3  GPIO and Interrupt Generation
        1. 8.3.3.1 I2C Daisy Chain
        2. 8.3.3.2 Programmable Interrupt Trigger
        3. 8.3.3.3 Internal Interrupt Signals
      4. 8.3.4  Sensor GPO Signals
      5. 8.3.5  Power-Up and Software Reset
      6. 8.3.6  Core Buck
        1. 8.3.6.1 Buck Converter Switching Frequency
        2. 8.3.6.2 Buck Converter Internal Current Limit and Short Detection
      7. 8.3.7  Low Dropout Voltage Regulators (LDOs)
        1. 8.3.7.1 LDO Output Capacitor Requirements
        2. 8.3.7.2 LDO Internal Current Limit and Short Detection
        3. 8.3.7.3 Dropout Voltage
      8. 8.3.8  WLED Boost Converter and WLED Drivers
        1. 8.3.8.1 WLED Driver Operation
        2. 8.3.8.2 WLED Modes
          1. 8.3.8.2.1 FLASH: MODE[1:0] = '00''
          2. 8.3.8.2.2 TORCH: MODE[1:0] = '01''
          3. 8.3.8.2.3 RED-EYE REDUCTION: MODE[1:0] = '10''
          4. 8.3.8.2.4 FOCUS ASSIST: MODE[1:0] = '11''
        3. 8.3.8.3 WLED Trigger Options
          1. 8.3.8.3.1 Level-Sensitive Flash Trigger (TRIG = 0)
            1. 8.3.8.3.1.1 Edge Trigger Flash (TRIG = 1)
        4. 8.3.8.4 Blanking (Tx-Mask) for Instantaneous Flash-Current Reduction
        5. 8.3.8.5 Voltage Mode
      9. 8.3.9  Indicator LED Operation
        1. 8.3.9.1 Retriggerable Pulse Extender
      10. 8.3.10 Safe Operation and Protection Features
        1. 8.3.10.1 LED Temperature Monitoring (Finger-Burn Protection)
        2. 8.3.10.2 LED Failure Modes (Open/Short Detection) and Overvoltage Protection
        3. 8.3.10.3 WLED Open Circuit Detection/Over Voltage Protection
        4. 8.3.10.4 LED Current Ramp-Up/Down
        5. 8.3.10.5 Short Circuit Protection
        6. 8.3.10.6 Hot Die Detection and Thermal Shutdown
      11. 8.3.11 WLED Boost Inductor Selection
      12. 8.3.12 I2C Bus Operation
        1. 8.3.12.1 Single Write to a Defined Location
        2. 8.3.12.2 Single Read From a Defined Location and Current Location
        3. 8.3.12.3 Sequential Read and Write
      13. 8.3.13 Subaddress Definition
        1. 8.3.13.1 I2C Device Address, Start and Stop Condition
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with a Single Input Power Rail
      2. 8.4.2 Sequencing the Input Power Rails
    5. 8.5 Register Map
      1. 8.5.1  GSTAT Register (address = 0x01) [reset = 00000000]
      2. 8.5.2  VRSTAT Register (address = 0x02) [reset = -]
      3. 8.5.3  VRSHORT Register (address = 0x03) [reset = 00000000]
      4. 8.5.4  INTMASK Register (address = 0x04) [reset = 00000000]
      5. 8.5.5  VCOSPEED Register (address = 0x05) [reset = 00000000]
      6. 8.5.6  POSTDIV2 Register (address = 0x06) [reset = 00000000]
      7. 8.5.7  BOOSTDIV Register (address = 0x07) [reset = 00000000]
      8. 8.5.8  BUCKDIV Register (address = 0x08) [reset = 00000000]
      9. 8.5.9  PLLSWR Register (address = 0x09) [reset = 00000000]
      10. 8.5.10 XTALDIV Register (address = 0x0A) [reset = 00000000]
      11. 8.5.11 PLLDIV Register (address = 0x0B) [reset = 00000000]
      12. 8.5.12 POSTDIV Register (address = 0x0C) [reset = 00000000]
      13. 8.5.13 PLLCTL Register (address = 0x0D) [reset = 10000000]
      14. 8.5.14 PLLCTL2 Register (address = 0x0E) [reset = 00000000]
      15. 8.5.15 CLKCFG1 Register (address = 0x0F) [reset = 00000000]
      16. 8.5.16 CLKCFG2 Register (address = 0x10) [reset = 00000000]
      17. 8.5.17 GPCTL0A Register (address = 0x14) [reset = 00000001]
      18. 8.5.18 GPCTL0B Register (address = 0x15) [reset = 00001000]
      19. 8.5.19 GPCTL1A Register (address = 0x16) [reset = 00000001]
      20. 8.5.20 GPCTL1B Register (address = 0x17) [reset = 00001000]
      21. 8.5.21 GPCTL2A Register (address = 0x18) [reset = 00000001]
      22. 8.5.22 GPCTL2B Register (address = 0x19) [reset = 00001000]
      23. 8.5.23 GPCTL3A Register (address = 0x1A) [reset = 00000001]
      24. 8.5.24 GPCTL3B Register (address = 0x1B) [reset = 00001000]
      25. 8.5.25 GPCTL4A Register (address = 0x1C) [reset = 00000001]
      26. 8.5.26 GPCTL4B Register (address = 0x1D) [reset = 00001000]
      27. 8.5.27 GPCTL5A Register (address = 0x1E) [reset = 00000001]
      28. 8.5.28 GPCTL5B Register (address = 0x1F) [reset = 00001000]
      29. 8.5.29 GPCTL6A Register (address = 0x20) [reset = 00000001]
      30. 8.5.30 GPCTL6B Register (address = 0x21) [reset = 00001000]
      31. 8.5.31 SGPO Register (address = 0x22) [reset = 00000000]
      32. 8.5.32 PITCTL Register (address = 0x23) [reset = 00000000]
      33. 8.5.33 WAKECFG Register (address = 0x24) [reset = 00000000]
      34. 8.5.34 IOWAKESTAT Register (address = 0x25) [reset = 00000000]
      35. 8.5.35 GPDI Register (address = 0x26) [reset = 00000000]
      36. 8.5.36 GPDO Register (address = 0x27) [reset = 00000000]
      37. 8.5.37 ILEDCTL Register (address = 0x28) [reset = 00000000]
      38. 8.5.38 WLEDSTAT Register (address = 0x29) [reset = 00000000]
      39. 8.5.39 VWLEDILIM Register (address = 0x2A) [reset = 00001010]
      40. 8.5.40 VWLEDVAL Register (address = 0x2B) [reset = 00000000]
      41. 8.5.41 WLEDMAXRER Register (address = 0x2C) [reset = 00000000]
      42. 8.5.42 WLEDMAXT Register (address = 0x2D) [reset = 00000000]
      43. 8.5.43 WLEDMAXAF Register (address = 0x2E) [reset = 00000000]
      44. 8.5.44 WLEDMAXF Register (address = 0x2F) [reset = 00000000]
      45. 8.5.45 WLEDTO Register (address = 0x30) [reset = 00000000]
      46. 8.5.46 VWLEDCTL Register (address = 0x31) [reset = 00111000]
      47. 8.5.47 WLEDTIMER_MSB Register (address = 0x32) [reset = 00000000]
      48. 8.5.48 WLEDTIMER_LSB Register (address = 0x33) [reset = 00000000]
      49. 8.5.49 WLEDC1 Register (address = 0x34) [reset = 00000000]
      50. 8.5.50 WLEDC2 Register (address = 0x35) [reset = 00000000]
      51. 8.5.51 WLEDCTL Register (address = 0x36) [reset = 00000000]
      52. 8.5.52 VCMVAL Register (address = 0x3C) [reset = 00000000]
      53. 8.5.53 VAUX1VAL Register (address = 0x3D) [reset = 00000000]
      54. 8.5.54 VAUX2VAL Register (address = 0x3E) [reset = 00000000]
      55. 8.5.55 VIOVAL Register (address = 0x3F) [reset = 00110100]
      56. 8.5.56 VSIOVAL Register (address = 0x40) [reset = 00110100]
      57. 8.5.57 VAVAL Register (address = 0x41) [reset = 00000000]
      58. 8.5.58 VDVAL Register (address = 0x42) [reset = 00000000]
      59. 8.5.59 S_I2C_CTL Register (address = 0x43) [reset = 00000000]
      60. 8.5.60 VCMCTL Register (address = 0x44) [reset = 00000000]
      61. 8.5.61 VAUX1CTL Register (address = 0x45) [reset = 00000000]
      62. 8.5.62 VAUX2CTL Register (address = 0x46) [reset = 00000000]
      63. 8.5.63 VACTL Register (address = 0x47) [reset = 00000000]
      64. 8.5.64 VDCTL Register (address = 0x48) [reset = 00000100]
      65. 8.5.65 RESET Register (address = 0x50) [reset = N/A]
      66. 8.5.66 REVID Register (address = 0xFF) [reset = 00100000]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Core Buck Design
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Output Capacitor
          3. 9.2.2.1.3 Input Capacitor
        2. 9.2.2.2 WLED Boost Design
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output Capacitor
          3. 9.2.2.2.3 Input Capacitor
        3. 9.2.2.3 LDOs Capacitor Selection
        4. 9.2.2.4 LED Selection
        5. 9.2.2.5 Recommended External Components
      3. 9.2.3 Application Performance Graphs
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Below is the layout check list.

● All input capacitors are placed as close as possible to the IC VIN and GND pins respectfully.

● A small 0.1-µF decoupling capacitor is recommended on each of the 3V3_VDD and 3V3_SUS pins.

● The cross sectional area loop from the input capacitor to the CORE input and CORE_GND pins is kept minimal.

● Route the feedback signal for the buck next to the current path of the buck converter. This decreases the cross sectional area of the feedback loop, minimizing noise injection into the loop.

● Ensure large planes for current to flow with minimum parasitics for all output rails and 3V3_VDD. Output rails include all LDOs, CORE_OUT, WLED_OUT and WLEDx.

● Ensure large planes for the ground return path for current to flow with minimum parasitics. Also, ground pours on the external and internal layers for ground improve the thermal performance.

● The PLL compensation components should be grounded to PLL_GND. The PLL ground loop must be kept minimal.

● If the GPIO3 pin is being driven with an external clock source, match the impedance of the GPIO3 trace to 50 Ω for best performance.

● Do not route any noise sensitive signals under or next to the inductor for the boost or buck converters. It is best to have a keepout region directly under the inductors or at least ground shielding.

● It is recommended to have the layer nearest to the side with the IC be a solid copper ground pour.

11.2 Layout Example

TPS68470 PCB_Layout.gif Figure 92. Layout