SBVS074M january   2007  – april 2023

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Other Orderable Devices (non-M3 Suffix)
    6. 6.6  Electrical Characteristics: Orderable Device with M3 suffix
    7. 6.7  Typical Characteristics: IOUT = 50 mA
    8. 6.8  Typical Characteristics: IOUT = 1 A
    9. 6.9  Typical Characteristics: IOUT = 50 mA (M3 Suffix)
    10. 6.10 Typical Characteristics: IOUT = 1 A (M3 Suffix)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable/Shutdown
      2. 7.3.2 Power Good
      3. 7.3.3 Internal Current Limit
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
    5. 7.5 Programming
      1. 7.5.1 Programmable Soft-Start
      2. 7.5.2 Sequencing Requirements
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Input, Output, and Bias Capacitor Requirements
      3. 8.1.3 Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Output Noise
    2. 8.2 Typical Applications
      1. 8.2.1 FPGA I/O Supply at 1.5 V With a Bias Rail
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 FPGA I/O Supply at 1.5 V Without a Bias Rail
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Estimating Junction Temperature
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics: Orderable Device with M3 suffix

at VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5.0 V, and TJ = –40°C to 125°C (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF Internal reference (Adj.) TA = +25°C 0.796 0.8 0.804 V
ΔVOUT(ΔVIN) Output voltage range VIN = 5 V, IOUT = 1.5 A VREF 3.6 V
ΔVOUT(ΔVIN) Accuracy(1) 2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 1.5 A –1 ±0.3 1 %
ΔVOUT(ΔIOUT) Line regulation VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V 0.001 %/V
VOUT Load regulation 50 mA ≤ IOUT ≤ 1.5 A 0.09 %/A
VDO VIN dropout voltage(2) IOUT = 1.5 A, VBIAS – VOUT(nom) ≥ 3.25 V(3) 50 95 mV
VBIAS dropout voltage(2) IOUT = 1.5 A, VIN = VBIAS 1.31 1.4 V
ICL Output current limit VOUT = 80% × VOUT(nom) 2 5.5 A
IBIAS BIAS pin current 1 1.2 mA
ISHDN Shutdown supply current (IGND) VEN ≤ 0.4 V 0.85 2.75 µA
IFB Feedback pin current –30 0.15 30 nA
PSRR Power-supply rejection (VIN to VOUT) 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 60 dB
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 30
Power-supply rejection (VBIAS to VOUT) 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 57
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 49
Vn Output noise voltage BW = 100 Hz to 100 kHz, IOUT = 1.5 A, CSS = 1 nF 20 μVrms x Vout
tSTR Minimum startup time RLOAD for IOUT = 1.0 A, CSS = open 250 µs
ISS Soft-start charging current VSS = 0.4 V 530 nA
VEN(hi) Enable input high level 1.1 5.5 V
VEN(lo) Enable input low level 0 0.4 V
VEN(hys) Enable pin hysteresis 55 mV
VEN(dg) Enable pin deglitch time 20 µs
IEN Enable pin current VEN = 5 V 0.1 0.25 µA
VIT PG trip threshold VOUT decreasing 85 90 94 %VOUT
VHYS PG trip hysteresis 2.5 %VOUT
VPG(lo) PG output low voltage IPG = 1 mA (sinking), VOUT < VIT 0.12 V
IPG(lkg) PG leakage current VPG = 5.25 V, VOUT > VIT 0.001 0.05 µA
TSD Thermal shutdown temperature Shutdown, temperature increasing 165 ℃
Reset, temperature decreasing 140
(1) Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
(3) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 6.29.