SBVS074L January   2007  – March 2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics IOUT = 50 mA
    7. 6.7 Typical Characteristics IOUT = 1 A
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable/Shutdown
      2. 7.3.2 Power Good
      3. 7.3.3 Internal Current Limit
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
    5. 7.5 Programming
      1. 7.5.1 Programmable Soft-Start
      2. 7.5.2 Sequencing Requirements
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Input, Output, and Bias Capacitor Requirements
      3. 8.1.3 Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Output Noise
    2. 8.2 Typical Applications
      1. 8.2.1 FPGA I/O Supply at 1.5 V With a Bias Rail
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 FPGA I/O Supply at 1.5 V Without a Bias Rail
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS74801 belongs to a family of low-dropout regulators that feature soft-start capability. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages.

The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology device, the output capacitor has little effect on loop stability. This architecture allows the TPS74801 to be stable with any capacitor type of value 2.2 μF or greater. Transient response is also superior to PMOS topologies, particularly for low VIN applications.

The TPS74801 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic start-up and limits startup inrush currents that may be caused by large capacitive loads. A power good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often required by processor-intensive systems.

8.1.1 Adjusting the Output Voltage

Figure 24 shows the typical application circuit for the TPS748 adjustable output device.

TPS748 ai_adj_app_cir_bvs074.gif Figure 24. Typical Application Circuit for the TPS748 (Adjustable)

R1 and R2 can be calculated for any output voltage using the formula shown in Figure 24. Table 3 lists sample resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R2 should be ≤ 4.99 kΩ.

Table 3. Standard 1% Resistor Values for Programming the Output Voltage(1)

R1 (kΩ) R2 (kΩ) VOUT (V)
Short Open 0.8
0.619 4.99 0.9
1.13 4.53 1.0
1.37 4.42 1.05
1.87 4.99 1.1
2.49 4.99 1.2
4.12 4.75 1.5
3.57 2.87 1.8
3.57 1.69 2.5
3.57 1.15 3.3
(1) VOUT = 0.8 × (1 + R1/R2).

SPACE

NOTE

When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately 50 μA of current from OUT. Although this condition does not cause any damage to the device, the output current may charge up the OUT node if total resistance between OUT and GND (including external feedback resistors) is greater than 10 kΩ.

8.1.2 Input, Output, and Bias Capacitor Requirements

The device is designed to be stable for all available types and values of output capacitors ≥ 2.2 μF. The device is also stable with multiple capacitors in parallel, which can be of any type or value.

The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To counteract any inductance in the input, the minimum recommended capacitor for VIN is 1 μF and minimum recommended capacitor for VBIAS is 0.1 µF. If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for VBIAS is 4.7 μF. Good quality, low ESR capacitors should be used on the input; ceramic X5R and X7R capacitors are preferred. These capacitors should be placed as close the pins as possible for optimum performance.

8.1.3 Transient Response

The TPS748 was designed to have excellent transient response for most applications with a small amount of output capacitance. In some cases, the transient response may be limited by the transient response of the input supply. This limitation is especially true in applications where the difference between the input and output is less than 300 mV. In this case, adding additional input capacitance improves the transient response much more than just adding additional output capacitance would do. With a solid input supply, adding additional output capacitance reduces undershoot and overshoot during a transient event; refer to Figure 20 in the Typical Characteristics section. Because the TPS748 is stable with output capacitors as low as 2.2 μF, many applications may then need very little capacitance at the LDO output. For these applications, local bypass capacitance for the powered device may be sufficient to meet the transient requirements of the application. This design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the LDO output.

8.1.4 Dropout Voltage

The TPS748 offers very low dropout performance, making it well-suited for high-current, low VIN/low VOUT applications. The low dropout of the TPS748 allows the device to be used in place of a dc/dc converter and still achieve good efficiency. Equation 4 provides a quick estimate of the efficiency.

Equation 4. TPS748 q_efficiency_bvs066.gif

This efficiency provides designers with the power architecture for their applications to achieve the smallest, simplest, and lowest cost solutions.

There are two different specifications for dropout voltage with the TPS748. The first specification (see Figure 25) is referred to as VIN Dropout and is used when an external bias voltage is applied to achieve low dropout. This specification assumes that VBIAS is at least 3.25 V(3) above VOUT, which is the case for VBIAS when powered by a 5.0-V rail with 5% tolerance and with VOUT = 1.5 V. If VBIAS is higher than VOUT +3.25 V(3), VIN dropout is less than specified.

The second specification (illustrated in Figure 31) is referred to as VBIAS Dropout and applies to applications where IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because VBIAS provides the gate drive to the pass FET; therefore, VBIAS must be 1.6 V above VOUT. Because of this usage, IN and BIAS tied together become a highly inefficient solution that can consume large amounts of power. Pay attention not to exceed the power rating of the IC package.

8.1.5 Output Noise

The TPS748 provides low output noise when a soft-start capacitor is used. When the device reaches the end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 1-nF soft-start capacitor, the output noise is reduced by half and is typically 30 μVRMS for a 1.2-V output (10 Hz to 100 kHz). Further increasing CSS has little effect on noise. Because most of the output noise is generated by the internal reference, the noise is a function of the set output voltage. The RMS noise with a 1-nF soft-start capacitor is given in Equation 5:

Equation 5. TPS748 q_vn_bvs074.gif

The low output noise of the TPS748 makes it a good choice for powering transceivers, PLLs, or other noise-sensitive circuitry.

8.2 Typical Applications

8.2.1 FPGA I/O Supply at 1.5 V With a Bias Rail

TPS748 ai_aux_bias_used_bvs074.gif Figure 25. Typical Application of the TPS748 Using an Auxiliary Bias Rail

8.2.1.1 Design Requirements

This application powers the I/O rails of an FPGA , at VOUT(nom) = 1.5 V and IOUT(dc) = 1.5 A. The available external supply voltages are 1.8 V, 3.3 V and 5 V.

8.2.1.2 Detailed Design Procedure

First, determine what supplies to use for the input and bias rails. A 1.8-V input can be stepped down to 1.5 V at 1.5 A if an external bias is provided, because the maximum dropout voltage is 165 mV if VBIAS is at least 3.25 V higher than VOUT. To achieve this voltage step, the bias rail is supplied by the 5-V supply. The approximation in Equation 4 estimates the efficiency at 83.3%.

The output voltage then must be set to 1.5 V. As Table 3 describes, set R1 = 4.12 kΩ and R2= 4.75 kΩ to obtain the required output voltage. The minimum capacitor sizing is desired to reduce the total solution size footprint; refer to Input, Output, and Bias Capacitor Requirements for CIN = 1 µF, CBIAS = 1 µF, and COUT = 2.2 µF. Use CSS = 1 nF for a typical 1.8-ms start-up time.

Figure 25 shows a simplified version of the final circuit.

8.2.1.3 Application Curves

TPS748 tc_vbias-trans_bvs074.gif Figure 26. VBIAS Line Transient
TPS748 tc_out_load_trans_bvs074.gif Figure 28. Output Load Transient Response
TPS748 tc_pwr_up_dwn_bvs074.gif Figure 30. Power-Up/Power-Down
TPS748 tc_vin-trans_bvs074.gif Figure 27. VIN Line Transient
TPS748 tc_turn_on_bvs074.gif Figure 29. Turnon Response

8.2.2 FPGA I/O Supply at 1.5 V Without a Bias Rail

TPS748 ai_aux_bias_none_bvs074.gif Figure 31. Typical Application of the TPS748 Without an Auxiliary Bias Rail

8.2.2.1 Design Requirements

The application powers the I/O rails of an FPGA, at VOUT(nom) = 1.5 V and IOUT(max) = 1.5 A. The only available rail is 3.3 V. The I/O pins are driven for only short durations with a 5% duty cycle, so thermal issues are not a concern.

8.2.2.2 Detailed Design Procedure

There is only one available rail; therefore, the input supply and the bias supply are connected together on the 3.3-V input supply.

The output voltage must be set to 1.5 V. As Table 3 describes, set R1 = 4.12 kΩ and R2= 4.75 kΩ to obtain the required output voltage. The minimum capacitor sizing is desired to reduce the total solution size footprint; refer to Input, Output, and Bias Capacitor Requirements for CIN = CBIAS = 4.7 µF, and COUT = 2.2 µF. Use CSS = 1 nF for a typical 1.8-ms start-up time.

Figure 31 shows the TPS748 configured without a bias rail.

8.2.2.3 Application Curves

TPS748 tc_vb_vdo-io_tmp_tj_bvs074.gif Figure 32. VBIAS Dropout Voltage vs IOUT and Temperature (TJ)
TPS748 tc_cur-vbias_vo_bvs074.gif Figure 34. Current Limit vs (VBIAS – VOUT)
TPS748 tc_vbias-frq_bvs074.gif Figure 33. VBIAS PSRR vs Frequency
TPS748 tc_vbias-trans_bvs074.gif Figure 35. VBIAS Line Transient