SBVS416B May   2022  – August 2022 TPS7A74

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Shutdown
      2. 7.3.2 Active Discharge
      3. 7.3.3 Global Undervoltage Lockout (UVLO) Circuit
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
    5. 7.5 Programming
      1. 7.5.1 Programmable Soft-Start
      2. 7.5.2 Sequencing Requirements
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Input, Output, and Bias Capacitor Requirements
      3. 8.1.3 Transient Response
      4. 8.1.4 Dropout Voltage
      5. 8.1.5 Output Noise
      6. 8.1.6 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 FPGA I/O Supply at 1.8 V With a Bias Rail
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Estimating Junction Temperature
      2. 8.4.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage drop on the input of the device during load transients, the capacitance on IN and BIAS must be connected as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can, therefore, improve stability. To achieve optimal transient performance and accuracy, the top side of R1 in Figure 8-1 must be connected as close as possible to the load. If BIAS is connected to IN, connect BIAS as close to the sense point of the input supply as possible. This connection minimizes the voltage drop on BIAS during transient conditions and can improve the turn-on response.

Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation (PD) of the device depends on input voltage and load conditions. Equation 9 calculates PD.

Equation 9. GUID-5A540FAA-8D3F-4136-9A31-08FC8C2775B5-low.gif

Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation.

On the WSON (DSD) package, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or left floating; however, this pad must be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device. Equation 10 calculates the maximum junction-to-ambient thermal resistance.

Equation 10. GUID-444A70E0-504A-47E5-8838-4F86395A7C38-low.gif
Note:

When the device is mounted on an application PCB, TI strongly recommends using ΨJT and Ψ