SBVS343A March   2019  – September 2019 TPS7A78


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Schematic Half-Bridge Configuration
      2.      Typical Schematic Full-Bridge Configuration
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Active Bridge Control
      2. 7.3.2 Full-Bridge (FB) and Half-Bridge (HB) Configurations
      3. 7.3.3 4:1 Switched-Capacitor Voltage Reduction
      4. 7.3.4 Undervoltage Lockout Circuits (VUVLO_SCIN) and (VUVLO_LDO_IN)
      5. 7.3.5 Dropout Voltage Regulation
      6. 7.3.6 Current Limit
      7. 7.3.7 Programmable Power-Fail Detection
      8. 7.3.8 Power-Good (PG) Detection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disabled Mode
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Input and Output Capacitors Requirements
      3. 8.1.3 Startup Behavior
      4. 8.1.4 Load Transient
      5. 8.1.5 Standby Power and Output Efficiency
      6. 8.1.6 Reverse Current
      7. 8.1.7 Switched-Capacitor Stage Output Impedance
      8. 8.1.8 Power Dissipation (PD)
      9. 8.1.9 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Calculating the Cap-Drop Capacitor CS
          1. CS Calculations for the Typical Design
        2. Calculating the Surge Resistor RS
          1. RS Calculations for the Typical Design
        3. Checking for the Device Maximum ISHUNT Current
          1. ISHUNT Calculations for the Typical Design
        4. Calculating the Bulk Capacitor CSCIN
          1. CSCIN Calculations for the Typical Design
        5. Calculating the PFD Pin Resistor Dividers for a Power-Fail Detection
          1. PFD Pin Resistor Divider Calculations for the Typical Design
        6. Summary of the Typical Application Design Components
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. Evaluation Module
        2. SIMPLIS Model
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Dissipation (PD)

To ensure proper thermal design, the printed circuit board (PCB) area around the TPS7A78 must include a minimal of heat-generating devices to avoid added thermal stress. The three internal sources that dissipate power are: the bridge rectifier conduction losses, the switched-capacitor stage, and the LDO. For devices with an output voltage greater 3.3 V, the maximum power dissipation under a maximum load current of 120 mA is estimated to be between 160 mW and 190 mW, assuming a nominal CS capacitor value for the given load current. For applications with less than a 3.3-V output , the power dissipated in the LDO is the dominant power and can be calculated using Equation 4 because the dropout voltage between VLDO_IN and VLDO_OUT can be as high as 2.7 V for the 1.3-V output option. See the Dropout Voltage Regulation section for details on dropout voltage.

Equation 4. PD_LDO = (VLDO_IN – VLDO_OUT) × IOUT

The higher dropout for less than 2.0-V output voltage options may run the device into thermal limitations at the startup ramp for higher temperatures, especially with the large LDO_OUT pin capacitor or when close to the maximum load. The thermal pad under the TPS7A78 must contain an array of filled vias that conduct heat to additional copper planes for increased heat dissipation. The amount of thermal dissipation determines the maximum allowable ambient temperature (TA) for the device. According to Equation 5, power dissipation and junction temperature are determined by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package as well as the temperature of the ambient air (TA).

Equation 5. TJ = TA + (RθJA × PD)

Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance, but not indicative of performance in any particular implementation.