SBVS197F May 2013 – October 2015 TPS7A8300
The TPS7A8300 is a low-noise, high PSRR, low-dropout regulator capable of sourcing a 2-A load with only
125 mV of maximum dropout. The TPS7A8300 can operate down to 1.1-V input voltage and 0.8-V output voltage. This combination of low noise, high PSRR, and low output voltage makes the device an ideal low dropout (LDO) regulator to power a multitude of loads from noise-sensitive communication components in high-speed communication applications to high-end microprocessors or field-programmable gate arrays (FPGAs).
The TPS7A8300 does not require external resistors to set output voltage, which is typical of adjustable low-dropout voltage regulators (LDOs). However, the TPS7A8300 uses pins 5, 6, 7, 9, 10, and 11 to program the regulated output voltage. Each pin is either connected to ground (active) or left open (floating). ANY-OUT programming is set by Equation 1 as the sum of the internal reference voltage (VREF = 0.8 V) plus the accumulated sum of the respective voltages assigned to each active pin; that is, 50mV (pin 5), 100mV (pin 6), 200mV (pin 7), 400mV (pin 9), 800mV (pin 10), or 1.6V (pin 11). Table 1 summarizes these voltage values associated with each active pin setting for reference. By leaving all program pins open, or floating, the output is thereby programmed to the minimum possible output voltage equal to VREF.
|ANY-OUT PROGRAM PINS (Active Low)||ADDITIVE OUTPUT VOLTAGE LEVEL|
|Pin 5 (50mV)||50 mV|
|Pin 6 (100mV)||100 mV|
|Pin 7 (200mV)||200 mV|
|Pin 9 (400mV)||400 mV|
|Pin 10 (800mV)||800 mV|
|Pin 11 (1.6V)||1.6 V|
Table 2 provides a full list of target output voltages and corresponding pin settings. The voltage setting pins have a binary weight; therefore, the output voltage can be programmed to any value from 0.8 V to 3.95 V in 50-mV steps.
There are several alternative ways to set the output voltage. The program pins can be driven using external general-purpose input/output pins (GPIOs), manually connected to ground using 0-Ω resistors (or left open), or hardwired by the given layout of the printed circuit board (PCB) to set the ANY-OUT voltage.
For output voltages greater than 3.95 V, use a traditional adjustable configuration (see the Adjustable Operation section).
The TPS7A8300 can be used either with the internal ANY-OUT network or using external resistors. Using the ANY-OUT network allows the TPS7A8300 to be programmed from 0.8 V to 3.95 V. To extend this range of output voltage operation to 5.0 V, external resistors must be used. This configuration is referred to as the adjustable configuration of the TPS7A8300 throughout this document. Regardless whether the internal resistor network or whether external resistors are used, the nominal output voltage of the device is set by two resistors, as shown in Figure 50. Using an internal resistor ensures a 1% matching and minimizes both the number of external components and layout footprint.
R1 and R2 can be calculated for any output voltage range using Equation 2. This resistive network must provide a current equal to or greater than 5 μA for optimum noise performance.
If greater voltage accuracy is required, take into account the output voltage offset contributions resulting from the feedback pin current (IFB) and use 0.1% tolerance resistors.
Table 3 shows the resistor combination required to achieve a few of the most common rails using commercially-available, 0.1%-tolerance resistors to maximize nominal voltage accuracy while abiding to the formula shown in Equation 2.
|FEEDBACK RESISTOR VALUES (1)|
|R1 (kΩ)||R2 (kΩ)|
Considering the use of the ANY-OUT internal network (where the unit resistance of 1R is equal to 6.05 kΩ) the output voltage is set by grounding the appropriate control pins, as shown in Figure 51. When grounded, all control pins add a specific voltage on top of the internal reference voltage (VREF = 0.8 V). The output voltage can be equated with Equation 4. Figure 51 and Figure 52 show a 1.2-V and 1-V output voltage, respectively, that provide an example of the circuit usage with and without BIAS voltage. These schematics are described in more detail in the Typical Application section.
The TPS7A8300 can be used either with the internal resistor network provided, or with the external component as a traditional adjustable LDO. Regardless of the implementation, the TPS7A8300 provides excellent regulation to 1% accuracy, excellent dropout voltage, and high output current capability.
If the input voltage is below 1.4 V, an external BIAS voltage must be supplied to maintain the dropout characteristics. The input voltage or the BIAS voltage is fed through to a internal charge pump to power the internal error amplifier providing the regulation.
Generally speaking, the dropout voltage often refers to the voltage difference between the input and output voltage (VDO = VIN – VOUT). However, in the , VDO is defined as the VIN – VOUT voltage at the rated current (IRATED), where the main current pass-FET is fully on in the ohmic region of operation and is characterized by the classic RDS(ON) of the FET. VDO indirectly specifies a minimum input voltage above the nominal programmed output voltage at which the output voltage is expected to remain within its accuracy boundary. If the input falls below this VDO limit (VIN < VOUT + VDO), then the output voltage decreases in order to follow the input voltage.
Dropout voltage is always determined by the RDS(ON) of the main pass-FET. Therefore, if the LDO operates below the rated current, then the VDO for that current scales accordingly. The RDS(ON) for the TPS7A8300 can be calculated using Equation 5:
Output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage stated as a percent. This accuracy error includes the errors introduced by the internal reference and the load and line regulation across the full range of rated load and line operating conditions over temperature, unless otherwise specified by the Electrical Characteristics. Output voltage accuracy also accounts for all variations between manufacturing lots.
The internal charge pump ensures proper operation without requiring an external BIAS voltage down to +1.4-V input voltage. Below a 1.4-V input voltage, a BIAS input voltage between 3.0 V and 6.5 V is required. Dropout plots in the ohmic region of the pass-FET are illustrated in the Typical Characteristics section (Figure 12 through Figure 17).
The TPS7A8300 includes a low-noise reference ensuring minimal noise during operation because the internal reference is normally the dominant term in noise analysis. Further noise reduction can be achieved using the NR/SS pin and by adding an external CFF between the SNS pin and the FB pin.
The undervoltage lockout (UVLO) circuit monitors the input and bias voltage (VIN and VBIAS, respectively) to prevent the device from turning on before VIN and VBIAS rise above the lockout voltage. The UVLO circuit also causes a shutdown when VIN and VBIAS fall below the lockout voltage.
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a thermal shutdown of the output.
A foldback feature limits the short-circuit current to protect the regulator from damage under all load conditions. If OUT is forced below 0 V before EN goes high and the load current required exceeds the foldback current limit, the device does not start up. In applications that function with both a positive and negative voltage supply, there are several ways to ensure proper start-up:
The TPS7A8300 contains a thermal shutdown protection circuit to turn off the output current when excessive heat is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (TJ) of the main pass-FET exceeds 160°C (typical). Thermal shutdown hysteresis assures that the LDO resets again (turns on) when the temperature falls to 140°C (typical). The thermal time-constant of the semiconductor die is fairly short, and thus the output cycles on and off at a high rate when thermal shutdown is reached until the power dissipation is reduced.
For reliable operation, limit the junction temperature to a maximum of 125°C. To estimate the thermal margin in a given layout, increase the ambient temperature until the thermal protection shutdown is triggered using worst-case load and highest input voltage conditions. For good reliability, thermal shutdown occurs at least 45°C above the maximum expected ambient temperature condition for the application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS7A8300 is designed to protect against thermal overload conditions. The circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A8300 into thermal shutdown degrades device reliability.
Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO exceed the respective threshold voltage. The noise-reduction capacitor (CNR/SS) serves a dual purpose of both governing output noise reduction and programming the soft-start ramp during turn-on. See the Application and Implementation section on implementing a soft-start.
The TPS7A8300 has a power-good function that works by toggling the state of the PG output pin. When the output voltage falls below the PG threshold voltage (VIT(PG)), the PG pin open-drain output engages (low impedance to GND). When the output voltage exceeds the VIT(PG) threshold by an amount greater than VHYS(PG), the PG pin becomes high-impedance. By connecting a pull-up resistor to an external supply, any downstream device can receive PG as a logic signal. Make sure that the external pull-up supply voltage results in a valid logic signal for the receiving device or devices. Use a pull-up resistor from 10 kΩ to 100 kΩ for best results.
When employing the feed-forward capacitor (CFF), the turn-on time-constant for the LDO is increased and the power-good output time-constant stays the same, resulting in an invalid status of the LDO. To avoid this issue and receive a valid PG output, ensure that the time-constant of both the LDO and the power-good output match. For more details, see application report, Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator, SBVA042.
An internal resistance network is provided allowing the TPS7A8300 output voltage to be programmed easily between 0.8 V to 3.95 V with a 50-mV step.
The TPS7A8300 requires a bias voltage on the BIAS pin ≥ 3.0 V if the high-current input supply voltage is between 1.1 to 1.4 V. The bias voltage pin consumes 2.3 mA, nominally.
If the input voltage is equal to, or exceeds 1.4 V, no bias voltage is necessary. The device is automatically selected to be powered from the IN pin in this condition and the BIAS pin can be left floating.
If the voltage on the EN pin is less than 0.5 V, the device is disabled and the output is high impedance. The output impedance of the LDO is then set by the gain setting resistors if a path to GND is provided between OUT and GND. Raising EN above 1.1 V (maximum) initiates the startup sequence of the device. In this state, quiescent current does not exceed 2.5 µA.