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TPS7A8300

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2-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good with high-accuracy

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2-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good with high-accuracy

TPS7A8300

ACTIVE
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Product details

Parameters

Output options Adjustable Output, Programmable Output Iout (Max) (A) 2 Vin (Max) (V) 6.5 Vin (Min) (V) 1.1 Vout (Max) (V) 5 Vout (Min) (V) 0.8 Noise (uVrms) 6 Iq (Typ) (mA) 2.8 Thermal resistance θJA (°C/W) 34 Approx. price (US$) 1.59 | 1ku Load capacitance (Min) (µF) 47 Rating Catalog Regulated outputs (#) 1 Features Enable, Output Discharge, Power Good, Soft Start Accuracy (%) 1 PSRR @ 100 KHz (dB) 40 Dropout voltage (Vdo) (Typ) (mV) 85 Operating temperature range (C) -40 to 125 open-in-new Find other Linear regulators (LDO)

Package | Pins | Size

VQFN (RGR) 20 12 mm² 3.5 x 3.5 VQFN (RGW) 20 25 mm² 5 x 5 open-in-new Find other Linear regulators (LDO)

Features

  • Ultralow Dropout: 125 mV Maximum at 2 A
  • Output Voltage Noise: 6 µVRMS
  • Power-Supply Ripple Rejection:
    • 40 dB at 1 MHz
  • Input Voltage Range:
    • Without BIAS: 1.4 V to 6.5 V
    • With BIAS: 1.1 V to 6.5 V
  • Two Output Voltage Modes:
    • ANY-OUT™ Version (User-Programmable Output via PCB Layout):
      • No External Resistor Required
      • Output Voltage Range: 0.8 V to 3.95 V
    • Adjustable Version:
      • Output Voltage Range: 0.8 V to 5.0 V
  • 1.0% Accuracy Over Line, Load, and Temperature
  • Stable with a 22-µF Output Ceramic Capacitor
  • Programmable Soft-Start Output
  • Power-Good (PG) Output
  • Available Packages:
    • 5-mm × 5-mm VQFN-20
    • 3.5-mm × 3.5-mm VQFN-20
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Description

The TPS7A8300 is a low-noise (6 µVRMS), low-dropout voltage regulator (LDO) capable of sourcing a 2-A load with only 125 mV of maximum dropout.

The TPS7A8300 output voltages are fully user-adjustable (up to 3.95 V) using a printed circuit board (PCB) layout without the need of external resistors, thus reducing overall component count. For higher output voltage applications, the device achieves output voltages up to 5 V with the use of external resistors. The device supports very low input voltages (down to 1.1 V) with the use of an additional BIAS rail.

With very high accuracy (1% over line, load, and temperature), remote sensing, and soft-start capabilities to reduce inrush current, the TPS7A8300 is ideal for powering high-current, low-voltage devices such as high-end microprocessors and field-programmable gate arrays (FPGAs).

The TPS7A8300 is designed to power-up noise-sensitive components in high-speed communication applications. The very low-noise, 6-µVRMS device output and high broad-bandwidth PSRR (40 dB at 1 MHz) minimizes phase noise and clock jitter in high-frequency signals. These features maximize performance of clocking devices, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs).

For applications where positive and negative low-noise rails are required, consider TI’s TPS7A33 family of negative high-voltage, ultralow-noise linear regulators.

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TPS7A89 ACTIVE 2-A, low-noise, high-accuracy, dual-channel adjustable ultra-low-dropout voltage regulator Dual-channel, low-noise, 2A LDO
TPS7A92 ACTIVE 2-A, low-noise, high-PSRR, adjustable ultra-low-dropout voltage regulator with high-accuracy 2-A, low noise (4.7uVrms) LDO in a small package (2.5 mm x 2.5mm)
Similar but not functionally equivalent to the compared device:
TPS7A83A ACTIVE 2-A, low-VIN (1.1-V), low-noise, high-accuracy, ultra-low-dropout voltage regulator with power good 2-A LDO with low-noise (4.4 µVrms) and low-dropout (200mV) and improved accuracy (0.75%)

Technical documentation

= Featured
No results found. Please clear your search and try again. View all 18
Type Title Date
* Datasheet TPS7A8300 2-A, 6-µVRMS, RF, LDO Voltage Regulator datasheet (Rev. F) Oct. 23, 2015
Application notes A Topical Index of TI LDO Application Notes (Rev. F) Jun. 27, 2019
Application notes Auxiliary circuits for high-performance audio Jan. 16, 2019
Technical articles LDO basics: capacitor vs. capacitance Aug. 01, 2018
Technical articles LDO Basics: Preventing reverse current Jul. 25, 2018
Technical articles LDO basics: introduction to quiescent current Jun. 20, 2018
Selection guides Low Dropout Regulators Quick Reference Guide (Rev. P) Mar. 21, 2018
Technical articles What is a low noise inverting buck converter? Oct. 30, 2017
User guides Power-Management-Laborkit LDO- Experimentierbuch (Rev. B) Sep. 19, 2017
Selection guides TI Components for Aerospace and Defense Guide (Rev. E) Mar. 22, 2017
User guides Cost Effective Test Methods Using PMLK LDO Boards (Rev. A) Aug. 31, 2016
User guides PMLK LDO Experiment Book (Rev. A) Aug. 31, 2016
White papers How to measure LDO noise Jul. 24, 2015
Application notes Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator Jul. 10, 2014
User guides TPS7A8300EVM-579 User's Guide Apr. 07, 2014
Selection guides Power Management for Xilinx FPGAs Feb. 04, 2014
User guides TPS7A8300EVM-209 Evaluation Module May 20, 2013
Application notes ANY-OUT™ LDO Controlled by I2C™ IO Expander Device (Rev. A) Sep. 20, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description
The ADS54J20EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J20 and LMK04828 clock jitter cleaner. The ADS54J20 is a low power, 12-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface (...)
Features
  • Flexible transformer coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS54J20 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)
View details
EVALUATION BOARDS Download
document-generic User guide
Description

The ADS54J40EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J40 and LMK04828 clock jitter cleaner. The ADS54J40 is a low power, 14-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface (...)

Features
  • Flexible transformer coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS54J40 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)
View details
EVALUATION BOARDS Download
document-generic User guide
Description
The ADS54J42EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J42 and LMK04828 clock jitter cleaner. The ADS54J42 is a low power, 14-bit, 625-GMSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)
Features
  • Flexible transformer coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS54J42 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)
View details
EVALUATION BOARDS Download
document-generic User guide
Description

The ADS54J69EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J69 and LMK04828 clock jitter cleaner. The ADS54J69 is a low power, 16-bit, 500-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

Features
  • Flexible transformer-coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS54J69 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)
View details
EVALUATION BOARDS Download
document-generic User guide
$20.00
Description
The TPS7A8300EVM-209 evaluation module (EVM) helps designers evaluate the operation and performance of the TPS7A8300, 2-A Low-Dropout Voltage Regulator for High Speed Communication Systems. The EVM circuit is configured to be a reference design for engineering applications requiring current to a (...)
Features
  • Ultra-Low Dropout: 125mV (max)
  • Very Good PSRR: Over 40dB up to 1MHz
  • Very Low Noise: 6µVRMS
  • Low Input Voltage Range without Bias: 1.4V to 6.5V
  • Low Input Voltage Range with Bias: 1.1V to 6.5V
  • ANY-OUT: No- Resistor, Configurable Output Voltage: 0.8V to 3.95V in 50mV step
  • 1.0% Accuracy over Line, Load and (...)
View details
EVALUATION BOARDS Download
document-generic User guide
$20.00
Description

The TPS7A8300EVM-579 evaluation module is designed for a typical configuration to evaluate the operation and performance of the TPS7A8300, 2-A low dropout voltage regulator for high speed communication systems.

The EVM circuit board is configured to be a reference design for engineering applications (...)

Features
  • Very low noise: 6 uVRMS
  • High PSRR: Over 40 dB up to 60 MHz
  • Ultra-low Dropout: 125mV (max)
  • Low Input Voltage Range: 1.4V to 6.5V (no bias rail), 1.1V to 6.5 (with bias rail)
  • ANY-OUT: No-Resistor, Configurable Output Voltage: 0.8V to 3.95V in 50mV step
View details
DEVELOPMENT KITS Download
document-generic User guide
$49.00
Description

Our TI-PMLK LDO experiment board is part of the TI Power Management Lab Kit (TI-PMLK) series. TI-PMLK series provides hands on learning to reinforce power supply knowledge. The modular format lets you customize the TI-PMLK series experience in a way that makes the most impact (...)

Features
  • Two different IC sections to expand the learning experience
  • Each section is configurable with jumpers for different exercises
  • The LDO board is accompanied by a downloadable LDO experiments book       
View details

Design tools & simulation

SIMULATION MODELS Download
SBAM414.ZIP (55 KB) - TINA-TI Reference Design
SIMULATION MODELS Download
SBVM356B.ZIP (50 KB) - PSpice Model
SIMULATION MODELS Download
SBVM380.TSC (57 KB) - TINA-TI Reference Design
SIMULATION MODELS Download
SBVM381.ZIP (8 KB) - TINA-TI Spice Model
SIMULATION MODELS Download
SBVM525.ZIP (2 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
Scalable 20.8 GSPS reference design for 12 bit digitizers
TIDA-010128 — This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems
TIDA-010122 — This reference design provides the solution for synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array RADAR and communication payload. The typical RF front end contains antenna, low noise amplifier (LNA (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer
TIDA-01028 — This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems
TIDA-01027 — This reference design demonstrates an efficient, low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers
TIDA-010131 — Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
TIDA-01023 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers
TIDA-01021 — High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers
TIDA-01024 — High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems
TIDA-01022 — This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Low-Voltage, Low-Noise Power-Supply Reference Design for Ultrasound Front End
TIDA-01466 — This reference design is a power supply optimized specifically for providing power to eight 16-channel receive AFE ICs for ultrasound imaging systems. This design reduces part count while maximizing efficiency by using single-chip DC-DC converter + LDO combo regulators to set the LDO input just (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High-Current Low-Noise Parallel LDO Reference Design
TIDA-01232 — This parallel low-dropout (LDO) reference design showcases the TPS7A85 low-noise LDO linear regulator in a parallel configuration, which is capable of sourcing 3.5 A per LDO or 7 A per board. Additional design flexibility includes the ability to stack this design to meet the current (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
16-Bit 1-GSPS Digitizer Reference Design with AC and DC Coupled Fixed Gain Amplifier
TIDA-00823 — This reference design discusses the use and performance of the Ultra-Wideband, Fixed-gain high-speed amplifier, the LMH3401 to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Quad-Channel, 12-Bit, 50-MSPS ADC Reference Design With Low Noise, Low Distortion, DC and AC Inputs
TIDA-00799 — This reference design demonstrates how to implement a single-ended-to-differential input path, which can be AC-coupled or DC-coupled for an ADC3422. It also explains how to design a high-input impedance, DC-coupled input path. The reference design can be used for applications such as low-power data (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
16-Bit 1-GSPS Digitizer Reference Design with AC and DC Coupled Variable Gain Amplifier
TIDA-00822 — This reference design discusses the use and performance of the Digital Variable-Gain high-speed amplifier, the LMH6401, to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

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VQFN (RGR) 20 View options
VQFN (RGW) 20 View options

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Training series

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Videos

LDO Architecture Review

This training gives an overview of the functional blocks internal to an LDO

Posted: 11-Jan-2017
Duration: 23:22

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