SBVS415A april   2023  – july 2023 TPS7A96

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Current Limit and Power-Good Threshold
      4. 7.3.4 Programmable Soft-Start (NR/SS Pin)
      5. 7.3.5 Precision Enable and UVLOs
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Output Voltage Restart (Overshoot Prevention Circuit)
      2. 8.1.2  Precision Enable (External UVLO)
      3. 8.1.3  Undervoltage Lockout (UVLO) Operation
      4. 8.1.4  Dropout Voltage (VDO)
      5. 8.1.5  Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
      6. 8.1.6  Adjusting the Factory-Programmed Current Limit
      7. 8.1.7  Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
      8. 8.1.8  Inrush Current
      9. 8.1.9  Optimizing Noise and PSRR
      10. 8.1.10 Adjustable Operation
      11. 8.1.11 Paralleling for Higher Output Current and Lower Noise
      12. 8.1.12 Recommended Capacitor Types
      13. 8.1.13 Load Transient Response
      14. 8.1.14 Power Dissipation (PD)
      15. 8.1.15 Estimating Junction Temperature
      16. 8.1.16 TPS7A96EVM-106 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Description

The TPS7A96 is an ultra-low noise (0.5 μVRMS), low-dropout (LDO) voltage regulator capable of sourcing 2 A with only 200 mV of dropout. The low dropout, in conjunction with a wide bandwidth error amplifier, allows for very high PSRR (104 dB at 1 kHz and 48 dB at 1 MHz) under low operating headroom (500 mV) and high output current (1.75 A).

The device output is adjustable from 0.4 V to 5.5 V with an external resistor. With the wide input voltage range, the device supports operation as low as 1.9 V and up to 5.7 V. The device includes a programmable current limit, programmable PG threshold, and precision enable, allowing better control in the application.

With the high-accuracy reference and wide-bandwidth topology, the device can be easily paralleled to achieve lower noise and higher current.

With 1% output voltage accuracy (over line, load, and temperature) and soft-start capabilities to reduce inrush current, the device is designed for powering sensitive analog low-voltage devices.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
TPS7A96 DSC (WSON, 10) 3 mm × 3 mm
For all available packages, see the orderable addendum at the end of the data sheet.
The package size (length × width) is a nominal value and includes pins, where applicable.

 

GUID-20230518-SS0I-ZSM1-19CK-NJPHWRBLHCQK-low.pngUltra-Low Output Noise Independent of Output Voltage (10 Hz–100 kHz)
GUID-20220802-SS0I-2NMN-XSRL-GB1Q2LBPLVRJ-low.gifTypical Application Circuit