SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

HBL Package PWP Package
14-Pin CFP 28-Pin HTSSOP
(Top View) (Top View)
GUID-20220809-SS0I-SBNV-K0KX-PPDCQFGZ0RDF-low.svg GUID-20220809-SS0I-SSKM-SLPG-1KB8JQK6W7XQ-low.svg
Table 5-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME HBL (14) NO. PWP (28) NO.
BIAS 1 3 I Bias supply. To support full output current, a separate bias supply is required if the headroom voltage is less than 1.6 V (Vheadroom = VIN – VOUT < 1.6 V). Set the separate bias supply to a voltage at least 1.6 V higher than VOUT for full output current support. A 12-V bias supply will satisfy these conditions (generally a 5-V supply will also suffice). There are no sequencing requirements between VBIAS and VIN. In order to limit noise on BIAS, an RC filter is recommended (typically 10 Ω and 4.7 μF) unless VBIAS is an ultra-clean supply. If a separate bias supply is not used, connect BIAS to VIN (it is also recommended to connect the VIN rail to the BIAS pin through an RC filter).
EN 2 4 I Enable. Driving this pin to logic high enables the device; driving the pin to logic low disables the device. If enable functionality is not required, connect this pin to IN. Do not float this pin.
IN 3, 4 6, 7, 8 I Input power. An input capacitor (nominally 10 μF) near this pin is recommended.
CLM 5 9 I Current limit mode. Connect CLM to VIN for brick-wall current limit mode (when current limit is reached, VOUT is regulated to maintain a constant output current until the fault is removed). Connect CLM to GND for turn-off current limit mode (when current limit is reached, VOUT stops regulating until EN is toggled). Do not change the value of this pin when the device is enabled, and do not float this pin.
GND 6 10, 11 — Ground.
PG 7 12 O Power good indicator. This is an open drain pin. Use a pull-up resistor to pull this pin up to VOUT or the desired logic level. It is recommended to pull down PG to ground if unused but it may be left floating.
REF 8 18 I/O Reference pin. REF outputs a nominal 1.2 V. Place a high accuracy 12.0-kΩ external resistor from REF to GND to set the internal 100-μA current source.
SS_SET 9 19 I/O Soft-start and voltage set pin. An external capacitor (nominally 4.7-μF ceramic) is used to slow down the output voltage ramp rate during startup along with filtering internal device noise. Capacitor values less than 4.7 μF will result in marginally higher output noise. There is internal fast start circuitry to enable reasonable soft start times.Additionally, a resistor from SS_SET to GND sets the output voltage. During nominal operation, 100 μA is output on this pin and a resistor from SS_SET to GND sets the output voltage.
STAB 10 20 I/O Stability pin. This is an output from the internal OTA (operational transconductance) error amplifier to aid in measuring or optimizing the control loop. Use a series capacitor (CCOMP) and resistor (RCOMP) of 4.7 nF and 5 kΩ to compensate the device. For different compensation options, view Section 8.3.8.2. A C0G (NP0) type capacitor capable of withstanding the lower of VBIAS or 7.5 V is recommended (for example, a 25-V rated capacitor).
OUT 11, 12 21, 22, 23 O Output power pin. The regulated output voltage. A single 220-µF or two 100-µF tantalum or tantalum polymer capacitors are recommended. See Section 8.3.8.1 for additional information.
OUTS 13 25 I Output sense pin. This pin is used to sense the output voltage for regulation. Connect OUTS to the OUT pin at the desired point of regulation (remote sense).
FB_PG 14 26 I Feedback and power good pin. The FB_PG pin enables setting of a configurable power good threshold. This is achieved by feeding the output voltage through a resistor divider to this pin (typical threshold of 300 mV). When the threshold is reached, PG is asserted. Additionally, when the threshold on this pin is reached, start-up is over and the internal fast start circuitry is disabled. If this pin is connected directly to OUT, fast start operation ceases and PG is asserted as soon as VOUT reaches 300 mV (typical).
NC 1, 2, 5, 13, 14, 15, 16, 17, 24, 27, 28 — No connect. This pin is not internally connected. It is recommended to connect these pins to GND to prevent charge buildup; however, these pins can also be left open or tied to any voltage between GND and VBIAS.
Thermal pad — The ceramic package thermal pad is internally connected to the backside of the die through an electrically conductive path and to the GND pin. It is recommended to connect this metal thermal pad to a large ground plane for effective heat dissipation.The plastic package thermal pad is connected to the backside of the die through an electrically conductive path, it is not internally grounded. Connect the thermal pad to a large ground plane for effective heat dissipation and to provide a connection of the backside of the die to GND for proper operation.
Metal lid Lid N/A — The lid is internally connected to the thermal pad and GND through the seal ring.
(1) I = Input, O = Output, I/O = Input or Output, — = Other