SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.10 PSRR

The PSRR (power supply rejection ratio) of the TPS7H1111, is the amount it attenuates the input noise at VIN, to the output, VOUT. It is mathematically defined in Equation 12.

Equation 12. PSRR = 20 × log(VIN(AC) / VOUT(AC))

The input noise is generally dominated by the switching ripple of an upstream converter. This noise occurs at the switching frequency and its harmonics.

The PSRR values are reported under various conditions and at different frequencies in both the Electrical Characteristics and the Typical Characteristics Figure 6-1 through Figure 6-11 . The TPS7H1111 is designed to have excellent PSRR across a wide variety of conditions. In order to further improve PSRR, operating conditions can be fine tuned. In general, the TPS7H1111 PSRR is most improved by the following (in relative order of importance):

  • Increased input supply headroom (increased VIN – VOUT)
  • Increased bias supply headroom (increased VBIAS – VOUT)
  • Decreased output current
  • Larger RC filter on the BIAS rail (only if the bias supply is the main source of noise)

PSRR is only minimally improved on the TPS7H1111 by the following:

  • Increased temperature
  • Increased soft start capacitance
  • Addition of a ferrite bead (see Section 9.2.1.3)
  • Increased input voltage
  • Increased output voltage

The TPS7H1111 architecture is optimized for high PSRR due to its high loop bandwidth. In order to keep the bandwidth high, the output capacitance should be within the recommended operating conditions. Traditional techniques to improved PSRR by increasing output capacitance are not valid. This is because additional capacitance could reduce the loop bandwidth of the TPS7H1111. This reduced bandwidth will degrade PSRR more than the capacitance helps.

If additional PSRR at high frequency (for example, > 10 MHz) is desired, a ferrite bead may be utilized. The ferrite bead should be placed outside the TPS7H1111 control loop as shown in Section 9.2.1 as to not degrade the loop bandwidth or stability.

In addition to the PSRR from VIN to VOUT, PSRR is specified from VBIAS to VOUT as PSRRBIAS. It is defined in Equation 13.

Equation 13. PSRRBIAS = 20 × log(VBIAS(AC) / VOUT(AC))

Since the BIAS supply is relatively low current, an RC filter can be inserted between the BIAS supply and BIAS pin (typically 10 Ω and 4.7 μF) to increase the PSRRBIAS. The RC filter, combined with the internal ripple rejection of the internal bias regulator, provides very high PSRRBIAS as shown in Figure 6-13. Therefore, at typical switching frequencies between 100 kHz and 1 MHz (where high ripple rejection is the most important to filter the input ripple), PSRRBIAS remains very high to avoid becoming a major limiting factor in overall device PSRR. If an RC filter is unable to be utilized, the PSRRBIAS values will be degraded as shown in Figure 6-12.

If the bias supply is exceptionally noisy or if an RC filter is unable to be utilized, it may be beneficial to calculate the total output ripple coming from the input ripple on both the VIN and VBIAS supplies. The total output ripple is the superposition of the VIN ripple attenuated by its PSRR and the VBIAS ripple attenuated by its PSRRBIAS as shown in Equation 14. Note however that each term is frequency dependent.

Equation 14. VOUT(AC) = VIN(AC) / (10PSRR/20) + VBIAS(AC) / (10PSRRBIAS/20)