SNVSCP5A April   2025  – August 2025 TPS7H3024-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SR_UVLO
      3. 8.3.3 SENSEx Inputs
        1. 8.3.3.1 VTH_SENSEX and VOUTx_RISE
        2. 8.3.3.2 IHYS_SENSEx and VOUTx_FALL
        3. 8.3.3.3 Input to Output Time Diagrams
        4. 8.3.3.4 Top and Bottom Resistive Divider Design Equations
      4. 8.3.4 MODE
      5. 8.3.5 Output Stages (RESETx, PWRGD, WDO, PULL_UP1 and PULL_UP2)
        1. 8.3.5.1 Push-Pull Outputs
      6. 8.3.6 WDI
      7. 8.3.7 User-Programmable TIMERS
        1. 8.3.7.1 DLY_TMR
        2. 8.3.7.2 WD_TMR
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Window Voltage Monitoring
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 SR_UVLO Threshold
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3.4 Top and Bottom Resistive Divider Design Equations

At the system level the designer knows (or selects) the VOUTx_RISE and VOUTx_FALL levels. Usually these voltages are selected as percentages of the nominal rail voltage (VOUTx) being monitored. Knowing this information, we can calculate the nominal resistive divider components values (RTOPx and RBOTTOMx) for the desired target levels. Using Equation 12 and Equation 13 we can calculate the top resistor as:

Equation 21. R T O P x   =   V OUTx_RISE - V OUTx_FALL I H Y S _ S E N S E x

From Equation 9 we can calculate the bottom resistor as:

Equation 22. R B O T T O M x   =   R T O P x × V T H _ S E N S E x V OUTx_RISE - V T H _ S E N S E x

It's important to notice that the larger the separation between VOUTx_RISE and VOUTx_FALL (referred to as VHYS_SENSEx), the bigger the error in the falling voltage. Figure 8-8 shows a plot of the error in the VOUTx_FALL for different sense hysteresis voltages (VHYS_SENSEx = VOUTx_RISE – VOUTx_FALL). The plot is created for three different VOUTx_RISE voltages (or percentages of the nominal output voltage as 90, 95, and 97% ) and two different output voltages (0.8V and 28V). As can be observed, the output voltage has very little impact on the falling voltage error (differences cannot be easily viewed on the plot). The error (in percent) can go from approximately 1% (at VHYS_SENSEx = 3%) to around 2.6% (at VHYS_SENSEx = 80%).

TPS7H3024-SP VOUTx_FALL Absolute Error vs VHYS_SENSEx Figure 8-8 VOUTx_FALL Absolute Error vs VHYS_SENSEx
A. This plot does not includes the error on the VOUTx_FALL due to the difference between the calculated top and bottom resistors using Equation 21 and Equation 22 and the actual resistance values that a designer can procure.
B. The resistor tolerance used for the calculation is 0.1%, VTH_SENSEx accuracy is 1%, and the IHYS_SENSEx accuracy is 3%.
C. In this plot the VHYS_SENSEx (%) represents the separation as percentages of the nominal output voltage (VOUTx).
D. In this plot, the VOUTx_FALL error in % is normalized with respect to the full-scale voltage (or VOUTx).