SNVSCP5A April   2025  – August 2025 TPS7H3024-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SR_UVLO
      3. 8.3.3 SENSEx Inputs
        1. 8.3.3.1 VTH_SENSEX and VOUTx_RISE
        2. 8.3.3.2 IHYS_SENSEx and VOUTx_FALL
        3. 8.3.3.3 Input to Output Time Diagrams
        4. 8.3.3.4 Top and Bottom Resistive Divider Design Equations
      4. 8.3.4 MODE
      5. 8.3.5 Output Stages (RESETx, PWRGD, WDO, PULL_UP1 and PULL_UP2)
        1. 8.3.5.1 Push-Pull Outputs
      6. 8.3.6 WDI
      7. 8.3.7 User-Programmable TIMERS
        1. 8.3.7.1 DLY_TMR
        2. 8.3.7.2 WD_TMR
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Window Voltage Monitoring
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 SR_UVLO Threshold
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1.2 Power-On Reset (VIN < VPOR_IN )

When the voltage on VIN is lower than the power on reset voltage (VPOR_IN), the output signal is undefined and is not to be relied for setting external deices to the correct logic level.

Figure 8-1 shows the RESETx outputs relationship to a rising input voltage (VIN). As can be observed, the RESETx are undefined when VIN is lower than VPOR_IN (typically 1.42V). During this time the outputs can be any value from 0V to VIN.

In this example, the input voltages to all input comparators (SENSEx) are below the VTH_SENSEx (typically 599.7mV). For this reason the RESETx, PWRGD and WDO stays low after VIN rises above UVLORISE (typically 2.79V).

TPS7H3024-SP Outputs in a Valid Low State After VIN > VPOR_IN Figure 8-1 Outputs in a Valid Low State After VIN > VPOR_IN
A. This figures assumes:
  1. A valid external pull-up voltage is connected to the PULL_UPx inputs (1.6V ≤ VPULL_UPx ≤ 7V).
  2. VIN(STEADY-SATE) is a valid VIN voltage between 3V to 14V.
  3. All inputs are assumed to be of undervoltage (UV) type for this graph.
  4. VOL represents: VOL_RESETx, VOL_PWRGD and VOL_WDO or the low logic output voltage for all outputs.