SNVSCP5A April   2025  – August 2025 TPS7H3024-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SR_UVLO
      3. 8.3.3 SENSEx Inputs
        1. 8.3.3.1 VTH_SENSEX and VOUTx_RISE
        2. 8.3.3.2 IHYS_SENSEx and VOUTx_FALL
        3. 8.3.3.3 Input to Output Time Diagrams
        4. 8.3.3.4 Top and Bottom Resistive Divider Design Equations
      4. 8.3.4 MODE
      5. 8.3.5 Output Stages (RESETx, PWRGD, WDO, PULL_UP1 and PULL_UP2)
        1. 8.3.5.1 Push-Pull Outputs
      6. 8.3.6 WDI
      7. 8.3.7 User-Programmable TIMERS
        1. 8.3.7.1 DLY_TMR
        2. 8.3.7.2 WD_TMR
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Window Voltage Monitoring
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 SR_UVLO Threshold
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

Over 3V ≤ VIN ≤ 14V, RDLY_TMR = 10kΩ, RREG_TMR = 10kΩ, VPULL_UP1 = 3.3V, VPULL_UP2 = 3.3V, over temperature range (TA = –55°C to 125°C) unless otherwise noted; includes group E radiation testing at TA = 25°C for RHA devices (1)
PARAMETER TEST CONDITIONS SUB-GROUP (2) MIN TYP MAX UNIT
tSTART_UP_DLY Start-up delay time (3) VREFCAP ≥ 1.1V, See Figure 7-1 1, 2, 3 0.3 2.8 ms
tpd_RESETx RESET propagation delay DLY_TMR = Open,
See Figure 7-2 and Figure 7-3
1, 2, 3

 0.62 4.3 µs
tpd_PWRGD PWRGD propagation delay DLY_TMR = Open,
See Figure 7-4
1, 2, 3

 0.51 4.3 µs
tpd_SR_UVLO SR_UVLO propagation delay  See Figure 7-5
1, 2, 3

 0.92 2 µs
tpd_WDI WDI propagation delay  See Figure 7-6 tWD_TMR = 0.52s
1, 2, 3

 23 40 µs
tWD_TMR = 1s 47 80
tWD_TMR = 1.5s 68 116
tPW_WDI WDI minimum pulse width  See Figure 7-7 4, 5, 6
2

 × tWD_OSC
tPW_SR_UVLO SR_UVLO minimum pulse width for valid reset  See Figure 7-8 4, 5, 6 0.61 1.1 µs
th_VENSEx_FAULT VSENSEx hold time for valid fault detection CLOAD = 100pF, See Figure 7-9 and
Figure 7-10		 4, 5, 6 0.56 2.2 µs
th_VENSEx_RISE Rising threshold on VSENSEx hold time See Figure 7-11 and Figure 7-12  4, 5, 6 3.7 µs
(1) See the 5962R24206 SMD (standard microcircuit drawing) for additional information on the RHA device.
(2) For subgroup definitions, see Quality Conformance Inspection table.
(3) During the power-on, VIN must be at or above UVLORISE(MAX) for at least tStart_up_delay for all internal references to be within specification.