SNVSCP5A April   2025  – August 2025 TPS7H3024-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SR_UVLO
      3. 8.3.3 SENSEx Inputs
        1. 8.3.3.1 VTH_SENSEX and VOUTx_RISE
        2. 8.3.3.2 IHYS_SENSEx and VOUTx_FALL
        3. 8.3.3.3 Input to Output Time Diagrams
        4. 8.3.3.4 Top and Bottom Resistive Divider Design Equations
      4. 8.3.4 MODE
      5. 8.3.5 Output Stages (RESETx, PWRGD, WDO, PULL_UP1 and PULL_UP2)
        1. 8.3.5.1 Push-Pull Outputs
      6. 8.3.6 WDI
      7. 8.3.7 User-Programmable TIMERS
        1. 8.3.7.1 DLY_TMR
        2. 8.3.7.2 WD_TMR
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Window Voltage Monitoring
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 SR_UVLO Threshold
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

With MODE=0, for all measurements referenced to the PWRGD voltage, the SENSEx voltage was forced in a non-fault state, unless otherwise specified.

TPS7H3024-SP tStart_up_delay Time Measurement
A. VIN(STEADY-STATE) is a valid operating voltage between 3V and 14V
Figure 7-1 tStart_up_delay Time Measurement
TPS7H3024-SP RESET1and RESET3 Propagation Delay (tpd_RESETx) Time MeasurementFigure 7-2 RESET1and RESET3 Propagation Delay (tpd_RESETx) Time Measurement
TPS7H3024-SP RESET2and RESET4 Propagation Delay (tpd_RESETx) Time Measurement
A. For tpd_RESETx each SENSEx propagation delay is measured independently.
Figure 7-3 RESET2and RESET4 Propagation Delay (tpd_RESETx) Time Measurement
TPS7H3024-SP PWRGD Propagation Delay (tpd_PWRGD) Figure 7-4 PWRGD Propagation Delay (tpd_PWRGD)
TPS7H3024-SP SR_UVLO Propagation Delay (tpd_SR_UVLO) Figure 7-5 SR_UVLO Propagation Delay (tpd_SR_UVLO)
TPS7H3024-SP WDI Propagation Delay (tpd_WDI)
A. MODE=0
Figure 7-6 WDI Propagation Delay (tpd_WDI)
TPS7H3024-SP WDI Pulse Width (tPW_WDI)
A. VSENSE1,3 = 1.5V; VSENSE2,4 = 0V
Figure 7-7 WDI Pulse Width (tPW_WDI)
TPS7H3024-SP SR_UVLO Pulse Width (tPW_SR_UVLO) Figure 7-8 SR_UVLO Pulse Width (tPW_SR_UVLO)
TPS7H3024-SP VSENSE1 and VSENSE3 hold time for valid fault detection (th_VSENSEx_FAULT)
A. For th_VSENSEx_FAULT each SENSEx is measured independently.
Figure 7-9 VSENSE1 and VSENSE3 hold time for valid fault detection (th_VSENSEx_FAULT)
TPS7H3024-SP VSENSE2 and VSENSE4 hold time for valid fault detection (th_VSENSEx_FAULT)
A. For th_VSENSEx_FAULT each SENSEx is measured independently.
Figure 7-10 VSENSE2 and VSENSE4 hold time for valid fault detection (th_VSENSEx_FAULT)
TPS7H3024-SP VSENSE1 and VSENSE3 Rising threshold hold time (th_VENSEx_RISE)
A. For th_VSENSEx_FAULT each SENSEx is measured independently.
Figure 7-11 VSENSE1 and VSENSE3 Rising threshold hold time (th_VENSEx_RISE)
TPS7H3024-SP VSENSE2 and VSENSE4 Rising threshold hold time (th_VENSEx_RISE)
A. For th_VSENSEx_FAULT each SENSEx is measured independently.
Figure 7-12 VSENSE2 and VSENSE4 Rising threshold hold time (th_VENSEx_RISE)