SLUSBZ6A April   2016  – August 2016 TPS92515 , TPS92515-Q1 , TPS92515HV , TPS92515HV-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Buck LED Driver Application
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. Table 1. Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  General Operation
      2. 8.3.2  Current Sense Comparator
      3. 8.3.3  OFF Timer
      4. 8.3.4  OFF-Timer, Shunt FET Dimming or Shunted Output Condition
      5. 8.3.5  Internal N-channel MOSFET
        1. 8.3.5.1 Drop-Out
      6. 8.3.6  VCC Internal Regulator and Undervoltage Lockout (UVLO)
      7. 8.3.7  Analog Adjust Input
        1. 8.3.7.1 IADJ Pin Clamp
        2. 8.3.7.2 IADJ Pin Clamp Characteristic
        3. 8.3.7.3 Analog Adjust (IADJ Pin) Control Methods
        4. 8.3.7.4 IADJ Control Method Notes
      8. 8.3.8  Thermal Protection
        1. 8.3.8.1 Maximum Output Current and Junction Temperature
      9. 8.3.9  Junction Temperature Relative Estimation
      10. 8.3.10 BOOT and BOOT UVLO
        1. 8.3.10.1 Start-Up, BOOT-UVLO and Pre-Charged Condition
      11. 8.3.11 PWM (UVLO and Enable)
        1. 8.3.11.1 Using PWM for UVLO (Undervoltage Lockout) Protection
          1. 8.3.11.1.1 UVLO Programming Resistors
        2. 8.3.11.2 Using PWM for Digitally Controlled Enable
        3. 8.3.11.3 UVLO: VIN, VCC and BOOT UVLO
        4. 8.3.11.4 Analog and PWM Dimming - Normalized Results and Comparison
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 General Design Procedure
        1. 9.2.1.1 Calculating Duty Cycle
        2. 9.2.1.2 Calculate OFF-Time Estimate
        3. 9.2.1.3 Calculate OFF-Time Resistor ROFF
        4. 9.2.1.4 Calculate the Minimum Inductance Value
        5. 9.2.1.5 Calculate the Sense Resistance
        6. 9.2.1.6 Calculate Input Capacitance
        7. 9.2.1.7 Calculate Output Capacitance
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Calculating Duty Cycle
        2. 9.2.3.2 Calculate OFF-Time Estimate
        3. 9.2.3.3 Calculate OFF-Time Resistor ROFF
        4. 9.2.3.4 Calculate the Inductance Value
        5. 9.2.3.5 Calculate the Sense Resistance
        6. 9.2.3.6 Calculate Input Capacitance
        7. 9.2.3.7 Verify Peak Current for Inductor Selection
        8. 9.2.3.8 Calculate Output Capacitance
        9. 9.2.3.9 Calculate UVLO Resistance Values
      4. 9.2.4 Application Curves
    3. 9.3 Dos and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Input Source Direct from Battery
    2. 10.2 Input Source from a Boost Stage
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
        1. 12.1.1.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

VIN = 40 V, –40°C ≤ TJ ≤ 150°C, VBOOT is referenced to SW pin, unless otherwise specified.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
PEAK CURRENT COMPARATOR
VCST VIN– VCSN peak current threshold VIADJ = VCC 224 240 251 mV
VIADJ = 2.2 V 211.5 220 223.5 mV
AADJ VIADJ to VIN – VCSN threshold gain 0.1 ≤ VIADJ ≤ 2.2 V 0.1 V/V
ICSN Current sense pin, input bias current –5 0 µA
tDEL CSN pin falling delay CSN fall to SW fall 75 130 ns
tLEB Minimum ON-time Minimum pulse width 75 195 275 ns
SYSTEM CURRENTS
Icq Operating current Not switching, VIADJ = VVCC 0.85 1.5 mA
INTEGRATED N-Channel MOSFET AND DRIVER
RDS(on) FET ON-resistance IDRN-SW = 200mA, VBOOT = 5 V,
TJ = 25°C		 290 500 mΩ
IDRN-SW = 200mA, VBOOT = 5 V,
TJ = 150°C		 290 600
IDRN-SW = 200mA, VBOOT = 3.5 V,
TJ = 25°C		 310 500
IDRN-SW = 200mA, VBOOT = 3.5 V,
TJ = 150°C		 310 650
IDRN-SW(off) FET leakage current VDRN-SW = 6 V, VSW = 0 V 10 µA
VBOOT-UVLO Voltage where gate drive is disabled VBOOT falling 2.0 2.8 3.5 V
VBOOT-UVLO(hys) BOOT pin UVLO Hysteresis 125 mV
IPD(PWM/UVLO) Pull down from SW when PWM low. PWM low, VBOOT = 5 V , VSW = 8 V 100 130 µA
IPD(BOOT) Pull down from SW when VBOOT reaches VBOOT-UVLO PWM high, VBOOT < BOOT-UVLO, VSW = 8 V 5 7 mA
IBOOT_Q BOOT pin quiescent current VBOOT = 5.5 V, 0 V ≤ VSW ≤ 65 V 60 90 µA
VCC/REFERENCE REGULATOR
VCC Regulated pin voltage IVCC(ext) ≤ 500 µA 4.8 5.0 5.2 V
VCCDO Drop out voltage IVCC(ext) ≤ 500 µA 0.1 0.2 V
VCCUVLO VCC undervoltage lockout Falling threshold, VIN = 10 V 4.0 4.2 4.4 V
VCCUVLO_hys VCC undervoltage lockout hysteresis 0.22 V
IVCC(ILIM) VCC regulator current limit VCC shorted to GND 14 19 23 mA
VINUVLO VIN UVLO Falling Threshold 4.65 4.90 5.15 V
VINUVLO_hys VIN UVLO Hysteresis 150 190 225 mV
OFF-TIMER
VOFT OFF-time threshold 0.95 1.00 1.05 V
tD(off) COFF threshold COFF to SW rising delay 68 120 ns
tOFF(max) Maximum OFF-time 230 µs
PWM/UVLO (Enable)
IPWM(uvlo) PWM/UVLO pin current VPWM(uvlo) = 5.5 V 10 nA
VPWM(uvlo) PWM/UVLO pin threshold PWM pin rising 0.95 1.0 1.05 V
VPWM(uvlo-hys) PWM/UVLO pin hysteresis Difference between rising and falling threshold 50 100 150 mV
tPWM(uvlo) PWM/UVLO pin delay PWM pin rising to SW pin rising 75 130 ns
PWM pin falling to SW pin falling 100 170 ns
IPWM(uvlo-hys) PWM/UVLO hysteresis current VPWM(uvlo) = 2 V –25 –20 –15 μA
THERMAL SHUTDOWN
TSD Thermal shutdown temperature 175 °C
TSD(hyst) Thermal shutdown hysteresis 10