SLVSHK8 December   2023 TPSM64406

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  CONFIG Device Configuration Pin
      4. 7.3.4  Adjustable Switching Frequency
      5. 7.3.5  Spread Spectrum
      6. 7.3.6  Adjustable Output Voltage (FB)
      7. 7.3.7  Input Capacitors
      8. 7.3.8  Output Capacitors
      9. 7.3.9  SYNC Allows Clock Synchronization and Mode Selection
      10. 7.3.10 Power-Good Output Voltage Monitoring
      11. 7.3.11 Bias Supply Regulator (VCC, VOSNS)
      12. 7.3.12 Overcurrent Protection (OCP)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – High-efficiency Dual Output 5 V at 3 A, 3.3 V at 3 A, Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Output Voltage Setpoint
          2. 8.2.1.2.2 Switching Frequency Selection
          3. 8.2.1.2.3 Input Capacitor Selection
          4. 8.2.1.2.4 Output Capacitor Selection
          5. 8.2.1.2.5 Other Considerations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 – High-efficiency 6 A Synchronous Buck Regulator for Industrial Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Output Voltage Setpoint
          2. 8.2.2.2.2 Switching Frequency Selection
          3. 8.2.2.2.3 Input Capacitor Selection
          4. 8.2.2.2.4 Output Capacitor Selection
          5. 8.2.2.2.5 Other Connections
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. 9 Custom Design With WEBENCH® Tools
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Enable EN Pin and Use as VIN UVLO

Apply a voltage less than 0.25 V to the EN1 pin to put the TPSM6440X into shutdown mode. In shutdown mode, the quiescent current drops to 0.5 µA (typical). Above this voltage but below the lower EN threshold, VCC is active but switching on SW1 and SW2 remains inactive. After EN1 is above VEN, the SW1 becomes active. EN2 controls switching on the second output SW2. In dual output configuration EN2 can be used to independently turn off the second output voltage, but does not control when the device enters shutdown mode. In single-output multiphase configuration EN1 on primaries and secondaries must be tied together. In single output configuration EN1 must not be used to disable the secondary devices for phase shedding. EN2 of the primary and secondaries must be tied together and can be used to shut down the secondary phases. The very high efficiency of the device in PFM operation eliminates the need to phase shed in most designs as phase of the secondaries is controlled even under PFM operation.

The EN terminals can not be left floating. The simplest method to enable the operation is to connect the EN pins to VIN. This action allows the self-start-up of the device when VIN drives the internal VCC above the UVLO level. However, many applications benefit from employing an enable divider string, which establishes a precision input undervoltage lockout (UVLO). The precision UVLO can be used for the following:

  • Sequencing
  • Preventing the device from retriggering when used with long input cables
  • Reducing the occurrence of deep discharge of a battery power source
Note that EN thresholds are accurate. The rising enable threshold has a 10% tolerance. Hysteresis is enough to prevent retriggering upon shutdown of the load (approximately 38%). The external logic output of another IC can also be used to drive the EN terminals, allowing system power sequencing.

GUID-796B8E66-348B-440A-8AF5-22CCB610A70D-low.gifFigure 7-2 VIN UVLO Using the EN Pin

Resistor values can be calculated using the following equations.

Equation 1. RENB=RENT×VEN(R) VIN(on)-VEN(R) 
Equation 2. VOFF=VIN(on)×1-VEN(H)

where

  • VON = VIN turn-on voltage
  • VOFF = VIN turn-off voltage