SLUSDN6A September   2019  – December 2020 TPSM82810 , TPSM82813

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Schematic
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Precise Enable (EN)
      2. 9.3.2 Output Discharge
      3. 9.3.3 COMP/FSET
      4. 9.3.4 MODE/SYNC
      5. 9.3.5 Spread Spectrum Clocking (SSC) - TPSM8281xS
      6. 9.3.6 Undervoltage Lockout (UVLO)
      7. 9.3.7 Power-Good Output (PG)
      8. 9.3.8 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pulse Width Modulation (PWM) Operation
      2. 9.4.2 Power Save Mode Operation (PFM/PWM)
      3. 9.4.3 100% Duty-Cycle Operation
      4. 9.4.4 Current Limit and Short Circuit Protection
      5. 9.4.5 Soft Start / Tracking (SS/TR)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Programming the Output Voltage
        2. 10.2.2.2 Feedforward capacitor
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Voltage Tracking
      2. 10.3.2 Synchronizing to an External Clock
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Thermal Consideration
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Over operating junction temperature (TJ = -40 °C to +125 °C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and TJ = 25 °C. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Operating Quiescent Current EN = high, IOUT = 0 mA, Device not switching 15 21 µA
ISD Shutdown Current EN = 0 V 0.11 18 µA
VUVLO Undervoltage Lockout Threshold Rising Input Voltage 2.5 2.6 2.75 V
Falling Input Voltage 2.25 2.5 2.6 V
TSD Thermal Shutdown Temperature Rising Junction Temperature 170 °C
Thermal Shutdown Hysteresis 15
CONTROL (EN, SS/TR, PG, MODE/SYNC)
VIH High Level Input Voltage for MODE/SYNC Pin 1.1 V
VIL Low Level Input Voltage for MODE/SYNC Pin 0.3 V
fSYNC Frequency Range on MODE/SYNC Pin for Synchronization 1.8 4 MHz
Duty Cycle of Synchronization Signal at MODE/SYNC Pin 40% 50% 60%
VIH Input Threshold Voltage for EN pin
Rising EN
 		 1.06 1.1 1.15 V
VIL Input Threshold Voltage for EN pin
Falling EN
 		 0.96 1.0 1.05 V
ILKG Input Leakage Current for EN, MODE/SYNC Pins EN, MODE/SYNC = VIN or GND 150 nA
VTH_PG UVP Power Good Threshold Rising (%VFB) 92% 95% 98%
UVP Power Good Threshold Falling (%VFB) 87% 90% 93%
OVP Power Good Threshold Rising (%VFB) 107% 110% 113%
OVP Power Good Threshold Falling (%VFB) 104% 107% 111%
Power Good De-glitch Time for a high level to low level transition on power good 40 µs
VOL_PG Power Good Output Low Voltage IPG = 2 mA 0.07 0.3 V
ILKG_PG Input Leakage Current for PG Pin VPG = 5 V 100 nA
ISS/TR SS/TR Pin Source Current 2.1 2.5 2.8 µA
Tracking Gain VFB / VSS/TR  1
Tracking Offset FB pin with VSS/TR = 0 V 17 mV
POWER SWITCH
RDS(ON) High-Side MOSFET ON-Resistance VIN ≥ 5 V 37 60 mΩ
RDS(ON) Low-Side MOSFET ON-Resistance VIN ≥ 5 V 15 35 mΩ
RDP Dropout resistance 100% mode. Maximum value at VIN = 3.3 V,   TJ = 85°C 50 90 mΩ
ILIMH High-Side MOSFET Current Limit (1) TPSM82810; VIN = 3 V to 6 V 4.8 5.6 6.55 A
ILIMH High-Side MOSFET Current Limit(1) TPSM82813; VIN = 3 V to 6 V 3.9 4.5 5.25 A
ILIMNEG Negative Current Limit (1) MODE/SYNC = HIGH -1.8 A
fS PWM Switching Frequency Range 1.8 2.25 4 MHz
fS PWM Switching Frequency
                 		 with COMP/FSET tied to VIN or GND 2.025 2.25 2.475 MHz
PWM Switching Frequency Tolerance using a resistor from COMP/FSET to GND -19% 18%
ton,min Minimum on-time VIN = 3.3 V 50 75 ns
toff,min Minimum off-time VIN = 3.3 V 30 ns
OUTPUT
VFB Feedback Voltage Accuracy VIN ≥ VOUT + 1 V; PWM mode 594 600 606 mV
VIN ≥ VOUT + 1 V; PFM mode 
VOUT ≥ 1.5 V; COUT,eff ≥ 27 μF		 594 600 612 mV
1 V ≤ VOUT < 1.5 V; PFM mode  COUT,eff ≥ 47 μF 594 600 615 mV
ILKG_FB Input Leakage Current (FB pin) VFB = 0.6 V 1 70 nA
VFB Feedback Voltage Accuracy with Voltage Tracking VIN ≥ VOUT + 1 V; PWM mode
VSS/TR = 0.3 V		 297 300 321 mV
Rdis Output Discharge Resistance 30 50 Ω
tdelay Start-up Delay Time IOUT = 0 mA, time from EN = high to start switching; VIN applied already 135 200 450 µs
tramp Ramp time; SS/TR Pin Open IOUT = 0 mA, time from first switching pulse until 95% of nominal output voltage 100 150 200 µs
(1) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And Short Circuit Protection section).