SLOS787J May   2012  – March 2020 TRF7964A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Terminal Functions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
      1. 6.1.1 RFID – Reader and Writer
    2. 6.2  System Block Diagram
    3. 6.3  Power Supplies
      1. 6.3.1 Supply Arrangements
      2. 6.3.2 Supply Regulator Settings
      3. 6.3.3 Power Modes
    4. 6.4  Receiver – Analog Section
      1. 6.4.1 Main and Auxiliary Receivers
      2. 6.4.2 Receiver Gain and Filter Stages
    5. 6.5  Receiver – Digital Section
      1. 6.5.1 Received Signal Strength Indicator (RSSI)
        1. 6.5.1.1 Internal RSSI – Main and Auxiliary Receivers
        2. 6.5.1.2 External RSSI
    6. 6.6  Oscillator Section
    7. 6.7  Transmitter – Analog Section
    8. 6.8  Transmitter – Digital Section
    9. 6.9  Transmitter – External Power Amplifier and Subcarrier Detector
    10. 6.10 TRF7964A IC Communication Interface
      1. 6.10.1 General Introduction
        1. 6.10.1.1 Continuous Address Mode
        2. 6.10.1.2 Noncontinuous Address Mode (Single Address Mode)
        3. 6.10.1.3 Direct Command Mode
        4. 6.10.1.4 FIFO Operation
      2. 6.10.2 Parallel Interface Mode
      3. 6.10.3 Reception of Air Interface Data
      4. 6.10.4 Data Transmission From MCU to TRF7964A
      5. 6.10.5 Serial Interface Communication (SPI)
        1. 6.10.5.1 Serial Interface Mode With Slave Select (SS)
      6. 6.10.6 Direct Mode
    11. 6.11 TRF7964A Initialization
    12. 6.12 Special Direct Mode for Improved MIFARE Compatibility
    13. 6.13 Direct Commands from MCU to Reader
      1. 6.13.1 Command Codes
        1. 6.13.1.1  Idle (0x00)
        2. 6.13.1.2  Software Initialization (0x03)
        3. 6.13.1.3  Reset FIFO (0x0F)
        4. 6.13.1.4  Transmission With CRC (0x11)
        5. 6.13.1.5  Transmission Without CRC (0x10)
        6. 6.13.1.6  Delayed Transmission With CRC (0x13)
        7. 6.13.1.7  Delayed Transmission Without CRC (0x12)
        8. 6.13.1.8  Transmit Next Time Slot (0x14)
        9. 6.13.1.9  Block Receiver (0x16)
        10. 6.13.1.10 Enable Receiver (0x17)
        11. 6.13.1.11 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
        12. 6.13.1.12 Test External RF (RSSI at RX Input with TX OFF) (0x19)
    14. 6.14 Register Description
      1. 6.14.1 Register Preset
      2. 6.14.2 Register Overview
      3. 6.14.3 Detailed Register Description
        1. 6.14.3.1 Main Configuration Registers
          1. 6.14.3.1.1 Chip Status Control Register (0x00)
          2. 6.14.3.1.2 ISO Control Register (0x01)
        2. 6.14.3.2 Control Registers – Sublevel Configuration Registers
          1. 6.14.3.2.1  ISO/IEC 14443 TX Options Register (0x02)
          2. 6.14.3.2.2  ISO/IEC 14443 High-Bit-Rate and Parity Options Register (0x03)
          3. 6.14.3.2.3  TX Timer High Byte Control Register (0x04)
          4. 6.14.3.2.4  TX Timer Low Byte Control Register (0x05)
          5. 6.14.3.2.5  TX Pulse Length Control Register (0x06)
          6. 6.14.3.2.6  RX No Response Wait Time Register (0x07)
          7. 6.14.3.2.7  RX Wait Time Register (0x08)
          8. 6.14.3.2.8  Modulator and SYS_CLK Control Register (0x09)
          9. 6.14.3.2.9  RX Special Setting Register (0x0A)
          10. 6.14.3.2.10 Regulator and I/O Control Register (0x0B)
        3. 6.14.3.3 Status Registers
          1. 6.14.3.3.1 IRQ Status Register (0x0C)
          2. 6.14.3.3.2 Interrupt Mask Register (0x0D) and Collision Position Register (0x0E)
          3. 6.14.3.3.3 RSSI Levels and Oscillator Status Register (0x0F)
          4. 6.14.3.3.4 Special Functions Register (0x10)
          5. 6.14.3.3.5 Special Functions Register (0x11)
          6. 6.14.3.3.6 Adjustable FIFO IRQ Levels Register (0x14)
        4. 6.14.3.4 Test Registers
          1. 6.14.3.4.1 Test Register (0x1A)
          2. 6.14.3.4.2 Test Register (0x1B)
        5. 6.14.3.5 FIFO Control Registers
          1. 6.14.3.5.1 FIFO Status Register (0x1C)
          2. 6.14.3.5.2 TX Length Byte1 Register (0x1D), TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7964A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 Layout Considerations
    3. 7.3 Impedance Matching TX_Out (Pin 5) to 50 Ω
    4. 7.4 Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.14.3.2.5 TX Pulse Length Control Register (0x06)

The length of the modulation pulse is defined by the protocol selected in the ISO Control register 0x01. With a high Q antenna, the modulation pulse is typically prolonged, and the tag detects a longer pulse than intended. For such cases, the modulation pulse length can be corrected by using the TX Pulse Length Control register (0x06). If the register contains all zeros, then the pulse length is governed by the protocol selection. If the register contains a value other than 0x00, the pulse length is equal to the value of the register in 73.7-ns increments. This means the range of adjustment can be 73.7 ns to 18.8 µs.

Table 6-27 describes the TX Pulse Length Control register.

Table 6-27 TX Pulse Length Control Register (0x06)

Function: Controls the length of TX pulse
Default: 0x00 at POR = H or EN = L and at each write to ISO Control register.
Bit Name Function Description
B7 Pul_p2 Pulse length MSB

The pulse range is 73.7 ns to 18.8 µs (1….255), step size 73.7 ns.

All bits low (00): pulse length control is disabled.

The following default timings are preset by the ISO Control register (0x01):

9.44 µs → ISO/IEC 15693 (TI Tag-It HF-I)

11 µs → Reserved

2.36 µs → ISO/IEC 14443 A at 106 kbps

1.4 µs → ISO/IEC 14443 A at 212 kbps

737 ns → ISO/IEC 14443 A at 424 kbps

442 ns → ISO/IEC 14443 A at 848 kbps; pulse length control disabled
B6 Pul_p1
B5 Pul_p0
B4 Pul_c4
B3 Pul_c3
B2 Pul_c2
B1 Pul_c1
B0 Pul_c0 Pulse length LSB