SBAS484B September   2010  – December 2016 TSC2014

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Electrical Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements for : I2C Standard Mode (fSCL = 100 kHz)
    7. 6.7  Timing Requirements for : I2C Fast Mode (fSCL = 400 kHz)
    8. 6.8  Timing Requirements for : I2C High-Speed Mode (fSCL = 1.7 MHz)
    9. 6.9  Timing Requirements for : I2C High-Speed Mode (fSCL = 3.4 MHz)
    10. 6.10 Timing Information
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Touch Screen Operation
      2. 7.3.2 4-Wire Touch Screen Coordinate Pair Measurement
      3. 7.3.3 Internal Temperature Sensor
      4. 7.3.4 Analog-to-Digital Converter
        1. 7.3.4.1 Data Format
        2. 7.3.4.2 Reference
        3. 7.3.4.3 Variable Resolution
        4. 7.3.4.4 Conversion Clock and Conversion Time
        5. 7.3.4.5 Touch Detect
        6. 7.3.4.6 Preprocessing
          1. 7.3.4.6.1 Preprocessing—Median Value Filter and Averaging Value Filter
        7. 7.3.4.7 Zone Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Interface
        1. 7.4.1.1 I2C Fast or Standard Mode (F/S Mode)
        2. 7.4.1.2 I2C High-Speed Mode (Hs Mode)
      2. 7.4.2 Touch Screen Measurements
        1. 7.4.2.1 Conversion Controlled by TSC2014 Initiated by TSC2014 (TSMode 1)
        2. 7.4.2.2 Conversion Controlled by TSC2014 Initiated by Host (TSMode 2)
        3. 7.4.2.3 Conversion Controlled by Host (TSMode 3)
    5. 7.5 Programming
      1. 7.5.1 Digital Interface
        1. 7.5.1.1 Address Byte
          1. 7.5.1.1.1 Bit D0: R/W
      2. 7.5.2 Start A Write Cycle
      3. 7.5.3 Register Access
      4. 7.5.4 Register Reset
    6. 7.6 Register Maps
      1. 7.6.1 R/W
      2. 7.6.2 Control Byte 0
      3. 7.6.3 Control Byte 1
        1. 7.6.3.1 Touch Screen Scan Function for XYZ or XY
          1. 7.6.3.1.1 C3-C0 = 0000 or 0001
        2. 7.6.3.2 Touch Screen Sensor Connection Tests for X-Axis and Y-Axis
          1. 7.6.3.2.1 C3-C0 = 1001
          2. 7.6.3.2.2 C3-C0 = 1010
        3. 7.6.3.3 Touch Sensor Short-Circuit Test
          1. 7.6.3.3.1 C3-C0 = 1011
          2. 7.6.3.3.2 C3-C0 = 1100
          3. 7.6.3.3.3 RM
          4. 7.6.3.3.4 SWRST
          5. 7.6.3.3.5 STS
      4. 7.6.4 Communication Protocol
        1. 7.6.4.1 Configuration Register 0
          1. 7.6.4.1.1 PSM
          2. 7.6.4.1.2 STS
          3. 7.6.4.1.3 RM
          4. 7.6.4.1.4 CL1, CL0
          5. 7.6.4.1.5 PV2-PV0
          6. 7.6.4.1.6 PR2-PR0
          7. 7.6.4.1.7 SNS2-SNS0
          8. 7.6.4.1.8 DTW
          9. 7.6.4.1.9 LSM
        2. 7.6.4.2 Configuration Register 1
          1. 7.6.4.2.1 TBM3-TBM0
          2. 7.6.4.2.2 BTD2-BTD0
      5. 7.6.5 Configuration Register 2
        1. 7.6.5.1 PINTS1 (default 0)
        2. 7.6.5.2 PINTS0 (default 0)
        3. 7.6.5.3 M1, M0, W1, W0 (default 0000)
        4. 7.6.5.4 TZ1 and TZ0, or AZ1 and AZ0 (default 00)
        5. 7.6.5.5 MAVE (default is 00000)
      6. 7.6.6 Converter Function Select Register
        1. 7.6.6.1 CFN15-CFN13
        2. 7.6.6.2 CFN12-CFN0
        3. 7.6.6.3 DAV Bits
        4. 7.6.6.4 RESET Flag
        5. 7.6.6.5 X CON
        6. 7.6.6.6 Y CON
        7. 7.6.6.7 Y SHR
        8. 7.6.6.8 PDST
        9. 7.6.6.9 ID[1:0]
      7. 7.6.7 Data Registers
        1. 7.6.7.1 X, Y, Z1, Z2, AUX, TEMP1 and TEMP2 Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Auxiliary and Temperature Measurement
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Supply Decoupling Capacitors
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description

Overview

The TSC2014 is an analog interface circuit for a human interface touch screen device. A register-based architecture eases integration with microprocessor-based systems through a standard I2C bus. All peripheral functions are controlled through the registers and onboard state machines. The TSC2014 features include:

  • Very low-power touch screen controller
  • Very small onboard footprint
  • Relieves host from tedious routine tasks by flexible preprocessing, saving resources for more critical tasks
  • Ability to work on very low supply voltage
  • Minimal connection interface allows easiest isolation and reduces the number of dedicated I/O pins required
  • Miniature, yet complete; requires no external supporting component.
  • Enhanced ESD protection

The TSC2014 consists of the following blocks (refer to the block diagram.

  • Touch Screen Interface
  • Auxiliary Input (AUX)
  • Temperature Sensor
  • Acquisition Activity Preprocessing
  • Internal Conversion Clock
  • I2C Interface

Functional Block Diagram

TSC2014 fbd_bas484.gif

Feature Description

Touch Screen Operation

A resistive touch screen operates by applying a voltage across a resistor network and measuring the change in resistance at a given point on the matrix where the screen is touched by an input (stylus, pen, or finger). The change in the resistance ratio marks the location on the touch screen.

The TSC2014 supports the resistive 4-wire configurations, as shown in Figure 16. The circuit determines location in two coordinate pair dimensions, although a third dimension can be added for measuring pressure.

4-Wire Touch Screen Coordinate Pair Measurement

A 4-wire touch screen is typically constructed as shown in Figure 16. It consists of two transparent resistive layers separated by insulating spacers.

TSC2014 construction_bas408.gif Figure 16. 4-Wire Touch Screen Construction

The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network. The A/D converter converts the voltage measured at the point where the panel is touched. A measurement of the Y position of the pointing device is made by connecting the X+ input to a data converter chip, turning on the Y+ and Y– drivers, and digitizing the voltage seen at the X+ input. The voltage measured is determined by the voltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+ lead does not affect the conversion because of the high input impedance of the A/D converter.

Voltage is then applied to the other axis, and the A/D converter converts the voltage representing the X position on the screen. This process provides the X and Y coordinates to the associated processor.

Measuring touch pressure (Z) can also be done with the TSC2014. To determine pen or finger touch, the pressure of the touch must be determined. Generally, it is not necessary to have very high performance for this test; therefore, 10-bit resolution mode is recommended (however, data sheet calculations are shown using the 12-bit resolution mode). There are several different ways of performing this measurement. The TSC2014 supports two methods. The first method requires knowing the X-plate resistance, the measurement of the X-Position, and two additional cross panel measurements (Z2 and Z1) of the touch screen (see Figure 17). Equation 1 calculates the touch resistance:

Equation 1. TSC2014 tcs2014_equation1.gif

The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-Position and Y-Position, and Z1. Equation 2 also calculates the touch resistance:

Equation 2. TSC2014 tcs2014_equation2.gif
TSC2014 press_meas_bas484.gif Figure 17. Pressure Measurement

When the touch panel is pressed or touched and the drivers to the panel are turned on, the voltage across the touch panel often overshoots and then slowly settles down (decays) to a stable dc value. This effect is a result of mechanical bouncing caused by vibration of the top layer sheet of the touch panel when the panel is pressed. This settling time must be accounted for, or else the converted value will be in error. Therefore, a delay must be introduced between the time the driver for a particular measurement is turned on, and the time a measurement is made.

In some applications, external capacitors may be required across the touch screen for filtering noise picked up by the touch screen (for example, noise generated by the LCD panel or back-light circuitry). The value of these capacitors provides a low-pass filter to reduce the noise, but will cause an additional settling time requirement when the panel is touched.

The TSC2014 offers several solutions to this problem. A programmable delay time is available that sets the delay between turning the drivers on and making a conversion. This delay is referred to as the panel voltage stabilization time, and is used in some of the TSC2014 modes. In other modes, the TSC2014 can be commanded to turn on the drivers only without performing a conversion. Time can then be allowed before the command is issued to perform a conversion.

The TSC2014 touch screen interface can measure position (X,Y) and pressure (Z). Determination of these coordinates is possible under three different modes of the A/D converter:

  • TSMode1 — conversion controlled by the TSC2014 initiated by the TSC;
  • TSMode2 — conversion controlled by the TSC2014 initiated by the host responding to the PENIRQ signal; or
  • TSMode3 — conversion completely controlled by the host processor.

Internal Temperature Sensor

In some applications, such as battery recharging, an ambient temperature measurement is required. The temperature measurement technique used in the TSC2014 relies on the characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic versus temperature. The ambient temperature can be predicted in applications by knowing the +25°C value of the VBE voltage and then monitoring the delta of that voltage as the temperature changes.

The TSC2014 offers two modes of temperature measurement. The first mode requires calibration at a known temperature, but only requires a single reading to predict the ambient temperature. The TEMP1 diode, shown in Figure 18, is used during this measurement cycle. This voltage is typically 580mV at +25°C with a 10μA current. The absolute value of this diode voltage can vary by a few millivolts; the temperature coefficient (TC) of this voltage is very consistent at –2.1mV/°C. During the final test of the end product, the diode voltage is stored at a known room temperature, in system memory, for calibration purposes by the user. The result is an equivalent temperature measurement resolution of 0.3°C/LSB (1LSB = 610μV with VREF = 2.5V).

TSC2014 fbd_temp_meas_bas484.gif Figure 18. Functional Block Diagram of Temperature Measurement Mode

The second mode does not require a test temperature calibration, but uses a two-measurement (differential) method to eliminate the need for absolute temperature calibration and for achieving 2°C/LSB accuracy. This mode requires a second conversion of the voltage across the TEMP2 diode with a resistance 91 times larger than the TEMP1 diode. The voltage difference between the first (TEMP1) and second (TEMP2) conversion is represented by:

Equation 3. TSC2014 tcs2014_equation3.gif

Where:

    N = the resistance ratio = 91.

    k = Boltzmann's constant = 1.3807 × 10-23 J/K (joules/kelvins).

    q = the electron charge = 1.6022 × 10-19 C (coulombs).

    T = the temperature in kelvins (K).

This method can provide much improved absolute temperature measurement, but a lower resolution of 1.6°C/LSB. The resulting equation to solve for T is:

Equation 4. TSC2014 tcs2014_equation4.gif

Where:

    ΔV = VBE (TEMP2) – VBE(TEMP1) (in mV).

    ∴ T = 2.573 ⋅ ΔV (in K),

    or T = 2.573 ⋅ ΔV – 273 (in °C).

Temperature 1 and/or temperature 2 measurements have the same timing as Figure 46.

Analog-to-Digital Converter

Figure 19 shows the analog inputs of the TSC2014. The analog inputs (X, Y, and Z touch panel coordinates, chip temperature and auxiliary inputs) are provided via a multiplexer to the Successive Approximation Register (SAR) Analog-to-Digital (A/D) converter. The A/D architecture is based on capacitive redistribution architecture, which inherently includes a sample-and-hold function.

TSC2014 simplified_bas484.gif
Untrimmed resistor; see the typical value in the
Figure 19. Simplified Diagram of the Analog Input Section

A unique configuration of low on-resistance switches allows an unselected A/D converter input channel to provide power and an accompanying pin to provide ground for driving the touch panel. By maintaining a differential input to the converter and a differential reference input architecture, it is possible to negate errors caused by the driver switch on-resistances.

The A/D converter is controlled by two A/D Converter Control registers. Several modes of operation are possible, depending on the bits set in the control registers. Channel selection, scan operation, preprocessing, resolution, and conversion rate may all be programmed through these registers. These modes are outlined in the sections that follow for each type of analog input. The conversion results are stored in the appropriate result register.

Data Format

The TSC2014 output data are in Straight Binary format as shown in Figure 20. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise.

TSC2014 ideal_iv_oc_bas408.gif
Reference voltage at converter: +REF – (–REF). See Figure 19.
Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 19.
Figure 20. Ideal Input Voltages and Output Codes

Reference

The TSC2014 uses an external voltage reference that applied to the VREF pin. It is possible to use VDD as the reference voltage because the upper reference voltage range is the same as the supply voltage range.

Variable Resolution

The TSC2014 provides either 10-bit or 12-bit resolution for the A/D converter. Lower resolution is often practical for measuring slow changing signals such as touch pressure. Performing the conversions at lower resolution reduces the amount of time it takes for the A/D converter to complete its conversion process, which also lowers power consumption.

Conversion Clock and Conversion Time

The TSC2014 contains an internal clock (oscillator) that drives the internal state machines that perform the many functions of the part. This clock is divided down to provide a conversion clock for the A/D converter. The division ratio for this clock is set in the A/D Converter Control register (see Table 14). The ability to change the conversion clock rate allows the user to choose the optimal values for resolution, speed, and power dissipation. If the 4MHz (oscillator) clock is used directly as the A/D converter clock (when CL[1:0] = (0,0)), the A/D converter resolution is limited to 10 bits. Using higher resolutions at this speed does not result in more accurate conversions. 12-bit resolution requires that CL[1:0] is set to (0,1) or (1,0).

Regardless of the conversion clock speed, the internal clock runs nominally at 3.8MHz at a 3V supply (VDD) and slows down to 3.6MHz at a 1.6V supply. The conversion time of the TSC2014 depends on several functions. While the conversion clock speed plays an important role in the time it takes for a conversion to complete, a certain number of internal clock cycles are needed for proper sampling of the signal. Moreover, additional times (such as the panel voltage stabilization time), can add significantly to the time it takes to perform a conversion. Conversion time can vary depending on the mode in which the TSC2014 is used. Throughout this data sheet, internal and conversion clock cycles are used to describe the amount of time that many functions take. These times must be taken into account when considering the total system design.

Touch Detect

PINTDAV can be programmed to generate an interrupt to the host. Figure 21 details an example for the Y-position measurement. While in the power-down mode, the Y– driver is on and connected to GND. The internal pen-touch signal depends on whether or not the X+ input is driven low. When the panel is touched, the X+ input is pulled to ground through the touch screen and the internal pen-touch output is set to low because of the detection on the current path through the panel to GND, which initiates an interrupt to the processor. During the measurement cycles for X- and Y-Position, the X+ input is disconnected, which eliminates any leakage current from the pull-up resistor to flow through the touch screen, thus causing no errors.

TSC2014 pentouch_irq_bas484.gif
Untrimmed resistor; see the typical value in the
Figure 21. Example of a Pen-Touch Induced Interrupt via the PINTDAV Pin

In modes where the TSC2014 must detect whether or not the screen is still being touched (for example, when doing a pen-touch initiated X, Y, and Z conversion), the TSC2014 must reset the drivers so that the RIRQ resistor is connected again. Because of the high value of this pull-up resistor, any capacitance on the touch screen inputs causes a long delay time, and may prevent the detection from occurring correctly. To prevent this possible delay, the TSC2014 has a circuit that allows any screen capacitance to be precharged, so that the pull-up resistor does not have to be the only source for the charging current. The time allowed for this precharge, as well as the time needed to sense if the screen is still touched, can be set in the configuration register.

This configuration underscores the need to use the minimum possible capacitor values on the touch screen inputs. These capacitors may be needed to reduce noise, but too large a value will increase the needed precharge and sense times, as well as the panel voltage stabilization time.

Preprocessing

The TSC2014 offers an array of powerful preprocessing operations that reduce unnecessary traffic on the bus and reduce the host processor loading. This reduction is especially critical for the serial interface, where limited bandwidth is a tradeoff, keeping the connection lines to a minimum.

All data acquisition tasks are looking for specific data that meet certain criteria. Many of these tasks fall into a predefined range, while other tasks may be looking for a value in a noisy environment. If these data are all to be retrieved by host processor for processing, the limited bus bandwidth quickly saturates, along with the host processor processing capability. In any case, the host processor must always be reserved for more critical tasks, not for routine work.

The preprocessing unit consists of two main functions: the combined MAV filter (median value filter and averaging filter), followed by the zone detection.

Preprocessing—Median Value Filter and Averaging Value Filter

The first preprocessing function, a combined MAV filter, can be operated independently as a median value filter (MVF), an averaging value filter (AVF), and a combined filter (MAVF).

If the acquired signal source is noisy because of the digital switching circuit, it may be necessary to evaluate the data without noise. In this case, the median value filter (MVF) operation helps to discard the noise. The array of N converted results is first sorted. The return value is either the middle (median value) of an array of M converted results, or the average value of a window size of W of converted results:

  • N = the total number of converted results used by the MAV filter
  • M = the median value filter size programmed
  • W = the averaging window size programmed

If M = 1, then N = W. A special case is W = 1, which means the MAVF is bypassed. Otherwise, if W > 1, only averaging is performed on these converted results. In either case, the return value is the averaged value of window size W of converted results. If M > 1 and W = 1, then N = M, meaning only the median value filter is operating. The return value is the middle position converted result from the array of M converted results. If M > 1 and W > 1, then N = M. In this case, W < M. The return value is the averaged value of middle portion W of converted results out of the array of M converted results. Since the value of W is an odd number in this case, the averaging value is calculated with the middle position converted result counted twice (so a total of W + 1 converted results are averaged).

Table 1. Median Value Filter Size Selection

M1 M0 MEDIAN VALUE FILTER
M =
POSSIBLE AVERAGING WINDOW SIZE
W =
0 0 1 1, 4, 8, 16
0 1 3 1
1 0 7 1, 3
1 1 15 1, 3, 7

Table 2. Averaging Value Filter Size Selection

AVERAGING VALUE FILTER SIZE SELECTION
W =
W1 W0 M = 1 (Averaging Only) M > 1
0 0 1 1
0 1 4 3
1 0 8 7
1 1 16 Reserved

NOTE

The default setting for MAVF is MVF (median value filter with averaging bypassed) for any invalid configuration. For example, if (M1, M0, W1, W0) = (1,0,1,0), the MAVF performs as it was configured for (1,0,0,0), median filter only with filter size = 7 and no averaging. The only exception is M > 1 and (W1, W0) = (1,1). This setting is reserved and should not be used.

Table 3. Combined MAV Filter Setting

M W INTERPRETATION N = OUTPUT
= 1 = 1 Bypass both MAF and AVF W The converted result
= 1 > 1 Bypass MVF only W Average of W converted results
> 1 = 1 Bypass AVF only M Median of M converted results
> 1 > 1 M > W M Average of middle W of M converted results with the median counted twice

The MAV filter is available for all analog inputs including the touch screen inputs, temperature measurements TEMP1 and TEMP2, and the AUX measurement.

TSC2014 mav_filtr_op_bas408.gif Figure 22. MAV Filter Operation (patent pending)

Zone Detection

The Zone Detection unit is capable of screening all processed data from the MAVF and retaining only the data of interest (data that fit the prerequisite). This unit can be programmed to send an alert if a predefined condition set by two threshold value registers is met. Three different zones may be set:

  1. Above the upper limit (X ≥ Threshold High)
  2. Between the two thresholds (Threshold Low < X < Threshold High)
  3. Below the lower limit (X ≤ Threshold Low)

The AUX and temperatures TEMP1 and TEMP2 have separate threshold value registers that can be enabled or disabled. This function is not available to the touch screen inputs. Once the preset condition is met, the DAV output to the PINTDAV pin is pulled low and the corresponding DAV bit is set.

Device Functional Modes

I2C Interface

The TSC2014 supports the I2C serial bus and data transmission protocol in all three defined modes: standard, fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a master. Devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The TSC2014 operates as a slave on the I2C bus. Connections to the bus are made via the open-drain I/O lines, SDA and SCL.

The following bus protocol has been defined (see Figure 23):

  • Data transfer may be initiated only when the bus is not busy.
  • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

    Bus Not Busy

    Both data and clock lines remain HIGH.

    Start Data Transfer

    A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.

    Stop Data Transfer

    A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.

    Data Valid

    The state of the data line represents valid data, when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.

    Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth-bit.

    Within the I2C bus specifications, a standard mode (100kHz clock rate), a fast mode (400kHz clock rate), and a high-speed mode (3.4MHz clock rate) are each defined. The TSC2014 works in all three modes.

    Acknowledge

    Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.

    A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

Figure 23 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible:

  1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte.
  2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, is transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned.

The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer ends with a STOP condition or a repeated START condition. Because a repeated START condition is also the beginning of the next serial transfer, the bus will not be released.

The TSC2014 may operate in the following two modes:

  1. Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit.
  2. Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data are transmitted on SDA by the TSC2014 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.

I2C Fast or Standard Mode (F/S Mode)

In I2C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Timing Information section.

In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with a START condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition on SDA while SCL is high, as shown in Figure 23. The bus is free for another transmission after a stop condition has occurred. Figure 23 shows the complete F/S mode transfer on the I2C, two-wire serial interface. The address byte, control byte, and data byte are transmitted between the START and STOP conditions. The SDA state is only allowed to change while SCL is low, except for the START and STOP conditions. Data are transmitted in 8-bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit word plus acknowledge bit).

TSC2014 tim_fast_stnd_bas408.gif Figure 23. Complete Fast- or Standard-Mode Transfer

I2C High-Speed Mode (Hs Mode)

Serial data transfer format in High-Speed (Hs) mode meets the Fast or Standard (F/S) mode I2C bus specification. Hs mode can only commence after the following conditions (all of which are in F/S mode) exist:

  1. START condition (S)
  2. 8-bit master code (00001xxx)
  3. not-acknowledge bit (N)

Figure 24 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only for triggering Hs mode, and are not to be used for slave addressing or any other purpose. The master code indicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet the Hs mode specification. Because no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge bit (N).

After the not-acknowledge bit (N) and SCL have been pulled up to a HIGH level, the master switches to Hs-mode and enables (at time tH; shown in Figure 24) the current-source pull-up circuit for SCL. Because other devices can delay the serial transfer before tH by stretching the LOW period of SCL, the master enables its current-source pull-up circuit when all devices have released SCL, and SCL has reached a HIGH level, thus speeding up the last part of the rise time of the SCL.

The master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit address, and receives an acknowledge bit (A) from the selected slave. After a repeated START (Sr) condition and after each acknowledge bit (A) or not-acknowledge bit (N), the master disables its current-source pull-up circuit. This disabling enables other devices to delay the serial transfer by stretching the LOW period of SCL. The master re-enables its current-source pull-up circuit again when all devices have released, and SCL reaches a HIGH level, which speeds up the last part of the SCL signal rise time.

Data transfer continues in Hs mode after the next repeated START (Sr), and only switches back to F/S mode after a STOP condition (P). To reduce the overhead of the master code, it is possible that a master links a number of Hs mode transfers, separated by repeated START conditions (Sr).

TSC2014 tim_high-speed_bas408.gif Figure 24. Complete High-Speed Mode Transfer

Touch Screen Measurements

As noted previously in the discussion of the A/D converter, several operating modes can be used that allow great flexibility for the host processor. This section examines these different modes.

Conversion Controlled by TSC2014 Initiated by TSC2014 (TSMode 1)

In TSMode 1, before a pen touch can be detected, the TSC2014 must be programmed with PSM = 1 and one of two scan modes:

  1. X-Y-Z Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0000); or
  2. X-Y Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0001).
  3. See Table 9 for more information on the converter function select bits.

When the touch panel is touched, and the internal pen-touch signal activates, the PINTDAV output is lowered if it is programmed as PENIRQ. The TSC2014 then executes the preprogrammed scan function without a host intervention.

At the same time, the TSC2014 starts up its internal clock. It then turns on the Y-drivers, and after a programmed panel voltage stabilization time, powers up the A/D converter and converts the Y coordinate. If preprocessing is selected, several conversions may take place. When data preprocessing is complete, the Y coordinate result is stored in a temporary register.

If the screen is still touched at this time, the X-drivers are enabled, and the process repeats, but measures the X coordinate instead, and stores the result in a temporary register.

If only X and Y coordinates are to be measured, then the conversion process is complete. A set of X and Y coordinates are stored in the X and Y registers. Figure 25 shows a flowchart for this process. The time it takes to go through this process depends upon the selected resolution, internal conversion clock rate, panel voltage stabilization time, precharge and sense times, and whether preprocessing is selected. The time needed to get a complete X and Y coordinate (sample set) reading can be calculated by:

Equation 5. TSC2014 tcs2014_equation5.gif

Where:

tCOORDINATE = time to complete X/Y coordinate reading.

tPVS = panel voltage stabilization time, as given in Table 15.

tPRE = precharge time, as given in Table 16.

tSNS = sense time, as given in Table 17.

N = number of measurements for MAV filter input, as given in Table 3 as N.

(For no MAV: M1-0[1:0] = '00', W1-0[1:0] = '00', N = 1.)

B = number of bits of resolution.

fOSC = TSC onboard OSC clock frequency. See for supply frequency (VDD).

fADC = A/D converter clock frequency, as given in Table 14.

OH1 = overhead time #1 = 2.5 internal clock cycles.

OHDLY1 = total overhead time for tPVS, tPRE, and tSNS = 10 internal clock cycles.

OHCONV = total overhead time for A/D conversion = 3 internal clock cycles.

LPPRO = preprocessor preprocessing time as given in Table 4.

Table 4. Preprocessing Delay

LPPRO =
M = W = FOR B = 12 BIT FOR B = 10 BIT
1 1, 4, 8, 16 2 2
3, 7 1 28 24
7 3 31 27
15 1 31 29
15 3 34 32
15 7 38 36
TSC2014 xy_tsmode1_bas408.gif Figure 25. Example of an X and Y Coordinate Touch Screen Scan Using TSMode 1

If the pressure of the touch is also to be measured, the process continues in the same way, but measuring the Z1 and Z2 values instead, and storing the results in temporary registers. Once the complete sample set of data (X, Y, Z1, and Z2) are available, they are loaded in the X, Y, Z1, and Z2 registers. This process is illustrated in Figure 26. As before, this process time depends upon the settings described above. The time for a complete X, Y, Z1, and Z2 coordinate reading is given by:

Equation 6. TSC2014 tcs2014_equation6.gif

Where:

OH2 = overhead time #2 = 3.5 internal clock cycles.

TSC2014 xyz_tsmode1_bas408.gif Figure 26. Example of an X, Y, and Z Coordinate Touch Screen Scan Using TSMode 1

Conversion Controlled by TSC2014 Initiated by Host (TSMode 2)

In TSMode 2, the TSC2014 detects when the touch panel is touched and causes the internal Pen-Touch signal to activate, which lowers the PINTDAV output if it is programmed as PENIRQ. The host recognizes the interrupt request, and then writes to the A/D Converter Control register to select one of the two touch screen scan functions:

  1. X-Y-Z Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0000); or
  2. X-Y Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0001).
  3. See Table 9 for more information on the converter function select bits.

The conversion process then proceeds as shown in Figure 27; see the previous sections for more details.

The main difference between this mode and the previous mode is that the host, not the TSC2014, decides when the touch screen scan begins.

The time needed to convert both X and Y coordinates under host control (not including the time needed to send the command over the I2C bus) is given by:

Equation 7. TSC2014 tcs2014_equation7.gif
TSC2014 xy_tsmode2_bas408.gif Figure 27. Example of an X and Y Coordinate Touch Screen Scan Using TSMode 2

Conversion Controlled by Host (TSMode 3)

In TSMode 3, the TSC2014 detects when the touch panel is touched and causes the internal Pen-Touch signal to be active, which lowers the PINTDAV output if it is programmed as PENIRQ. The host recognizes the interrupt request. Instead of starting a sequence in the TSC2014, which then reads each coordinate in turn, the host must now control all aspects of the conversion. Generally, upon receiving the interrupt request, the host turns on the X drivers.

NOTE

If drivers are not turned on, the device detects this condition and turns them on before the scan starts. This situation is why the event of Turn On Drivers is shown as optional in Figure 28 and Figure 29.

After waiting for the settling time, the host then addresses the TSC2014 again, this time requesting an X coordinate conversion.

The process is then repeated for the Y and Z coordinates. The processes are outlined in Figure 28 and Table 5. Figure 28 shows two consecutive scans on X and Y. Figure 29 shows a single Z scan.

The time needed to convert any single coordinate X or Y under host control (not including the time needed to send the command over the I2C bus) is given by:

Equation 8. TSC2014 tcs2014_equation8.gif

Where:

OHDLY2 = total overhead time for tPRE and tSNS = 6 internal clock cycles.

TSC2014 xy_tsmode3_bas408.gif Figure 28. Example of X and Y Coordinate Touch Screen Scan Using TSMode 3

The time needed to convert any Z1 and Z2 coordinate under host control (not including the time needed to send the command over the I2C bus) is given by:

Equation 9. TSC2014 tcs2014_equation9.gif
TSC2014 z_tsmode3_wo_bas408.gif Figure 29. Example of Z1 and Z2 Coordinate Touch Screen Scan
(without Panel Stabilization Time) Using TSMode 3

If the drivers are not turned on before the touch screen scan mode is programmed, the panel stabilization time should be included. In this case, the time needed to convert any single X or Y under host control (not including the time needed to send the command over the I2C bus) is given by:

Equation 10. TSC2014 tcs2014_equation10.gif
TSC2014 z_tsmode3_with_bas408.gif Figure 30. Example of a Z1 and Z2 Coordinate Touch Screen Scan
(with Panel Stabilization Time) Using TSMode 3

The time needed to convert any single coordinate (either X or Y) under host control (not including the time needed to send the command over the I2C bus) is given by:

Equation 11. TSC2014 tcs2014_equation11.gif
TSC2014 x_tsmode3_bas408.gif Figure 31. Example of a Single X Coordinate Touch Screen Scan
(with Panel Stabilization Time) using TSMode 3

Programming

Digital Interface

Address Byte

The TSC2014 has a 7-bit slave address word. The first six bits (MSBs) of the slave address are factory-preset to comply with the I2C standard for A/D converters and are always set at '100100'. The logic state of the address input pin determines the LSB of the device address to activate communication. Therefore, a maximum of two devices with the same preset code can be connected on the same bus at one time.

The AD0 address input is only read during a power-up of the device, and should be connected to supply (VDD/REF) or ground (GND). The slave address is latched into the TSC2014 on the falling edge of SCL after the read/write bit has been received by the slave.

The last bit of the address byte (R/W) defines the operation to be performed. When set to a '1', a read operation is selected; when set to a ‘0’, a write operation is selected. Following the START condition, the TSC2014 monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the '10010' code, the appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.

Table 5. I2C Slave Address Byte

MSB
D7
D6 D5 D4 D3 D2 D1 LSB
D0
1 0 0 1 0 0 AD0 R/W

Bit D0: R/W

1: I2C master read from TSC (I2C read addressing).

0: I2C master write to TSC (I2C write addressing).

TSC2014 i2c_bus_addr_bas484.gif Figure 32. I2C Bus Addressing (Slave Address Byte Format)

Start A Write Cycle

A write cycle begins when the master issues the slave address to the TSC2014. The slave address consists of seven address bits and a write bit (R/W = 0; see Table 5). When the eighth bit has been received and the address matches the AD0 address input pin setting, the TSC2014 issues an acknowledge bit by pulling SDA low for one additional clock cycle (ACK = 0); see Figure 32.

When the master receives the acknowledge bit from the TSC2014, the master writes the input control byte to the slave; see Table 5. After the control byte is received by the slave, the slave issues another acknowledge bit by pulling SDA low for one clock cycle (ACK = 0). The master then ends the write cycle by issuing a STOP or repeated START condition; see Figure 33.

TSC2014 write_cycle_bas408.gif Figure 33. Write Cycle

Register Access

Data access begins with the master issuing a START (or repeated START) condition followed by the 7-bit address and a read bit (R/W = 1; see Table 5). When the eighth bit has been received and the address matches, the slave issues an acknowledge by pulling SDA low for one clock cycle (ACK = 0). The first byte of serial data then follows. After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge (ACK = 0). The slave issues the second byte of serial data upon receiving the acknowledgment from the master (D7-D0), followed by a not-acknowledge bit (ACK = 1) from the master to indicate that the last data byte has been received. The master then issues a STOP condition (P) or repeated START (Sr), which ends the read cycle, as shown in Figure 34 and Figure 35. If the master issues a not-acknowledge (ACK = 1) after receipt of the first data byte, the master must then issue a stop condition (P) to reset the registers. If the master is not ready to receive the second data byte, it should issue the acknowledge (ACK = 0), or the master should stretch the clock. Upon restart of the clock, the second byte of data can be received by the master.

TSC2014 read_cycle_seq_bas408.gif Figure 34. Sequential Read Cycle
TSC2014 read_cycle_rep_bas408.gif Figure 35. Repeated Read Cycle

Register Reset

There are three way to reset the TSC2014.

  • First: At power-on, a power good signal generates a prolonged reset pulse internally to all registers.
  • Second: An external pin, RESET, is available to perform a system reset or allow other peripherals (such as a display) to reset the device if the pulse meets the timing requirement (at least 10μs wide). Any RESET pulse less than 5μs will be rejected. To accommodate the timing drift between devices because of process variation, a RESET pulse width between 5μs to 10μs falls into the gray area that is not recognized, and the result is undetermined; this situation should be avoided. Refer to Figure 36 for details. A good reset pulse must be low for at least 10 μs. There is an internal spike filter to reject spikes up to 20ns wide.
  • TSC2014 tim_ext_rst_bas408.gif
    NOTE: See for more information.
    Figure 36. External Reset Timing
  • Third: A software reset can be activated by writing a '1' to CB1.1 (bit 1 of control byte 1). It should be noted this reset is not self-clearing so the user must write a '0' to remove the software reset.

A reset clears all registers and loads default values. A power-on reset and external (hardware) reset take precedence over a software reset. If a software reset is not cleared by the user, it is cleared by either a power-on reset or an external (hardware) reset.

NOTE

It is required to have the host issue a hardware reset to the TSC2014 after the device power is good and stable to ensure all the registers initialized properly.

Register Maps

R/W

Register read and write control. A '1' indicates that the value of the internal register address bits A3-A0 is stored internally as the starting address for a register read (see Figure 33). The content of the addressed register is sent to SDA by using I2C read addressing (see Figure 34 and Figure 35). A '0' indicates that the data following Control Byte 0 on SDA are written into the internal register addressed by bits A3-A0 (see Figure 33).

Control Byte 0

Figure 37. Control Byte Format:
Start a Conversion and Mode Setting
MSB
D7
D6 D5 D4 D3 D2 D1 LSB
D0
(Control Byte 0) A3 A2 A1 A0 Reserved
(Write '0')
PND0 R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. Control Byte 0 Bit Register Description (D7 = 0)

Bit Field Type Reset Description
D7 Control Byte ID R/W 0000h 1: Control Byte 1 (start conversion and channel select and conversion-related configuration).
0: Control Byte 0 (read/write data registers and non-conversion-related controls).
D6 A3 R 0000h Register Address Bits as detailed in Table 7
D5 A2 R 0000h
D4 A1 R 0000h
D3 A0 R 0000h
D2 RESERVED R 0000h A '0' must be set in this bit for normal operation
D1 PND0 R/W 0000h Power Not Down Control
1: A/D converter biasing circuitry is always on between conversions but is shut down after the converter function stops.
0: A/D converter biasing circuitry is shut down either between conversions or after the converter function stops
D0 R/W R/W 0000h TSC Internal Register Data Flow Control
1: Set the starting address of the TSC internal registers for a register read (see Figure 33)
0: Write to TSC internal registers

Table 7. Internal Register Map

REGISTER ADDRESS REGISTER CONTENT READ/WRITE
A3 A2 A1 A0
0 0 0 0 X measurement result R
0 0 0 1 Y measurement result R
0 0 1 0 Z1 measurement result R
0 0 1 1 Z2 measurement result R
0 1 0 0 AUX measurement result R
0 1 0 1 Temp1 measurement result R
0 1 1 0 Temp2 measurement result R
0 1 1 1 Status R
1 0 0 0 AUX high threshold R/W
1 0 0 1 AUX low threshold R/W
1 0 1 0 Temp high threshold (apply to both TEMP1 and TEMP2) R/W
1 0 1 1 Temp low threshold (apply to both TEMP1 and TEMP2) R/W
1 1 0 0 CFR0 R/W
1 1 0 1 CFR1 R/W
1 1 1 0 CFR2 R/W
1 1 1 1 Converter function select status R

Control Byte 1

Figure 38. Control Byte Format:
Start a Conversion and Mode Setting
MSB
D7
D6 D5 D4 D3 D2 D1 LSB
D0
(Control Byte 1) C3 C2 C1 C0 RM SWRST STS
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. Control Byte 1 Bit Register Description (D7 = 1)

Bit Field Type Reset Description
D7 Control Byte ID R/W 0000h 1: Control Byte 1 (start conversion and channel select and conversion-related configuration).
0: Control Byte 0 (read/write data registers and non-conversion-related controls).
D6 C3 R 0000h Converter function select bits. These bits select the input to be converted, and the converter function to be executed. Table 9 lists the possible converter functions.
D5 C2 R 0000h
D4 C1 R 0000h
D3 C0 R 0000h
D2 RM R/W 0000h 0: 10 Bit
1: 12 Bit
D1 SWRST R/W 0000h Software Reset. This bit is self-clearing.
1: Reset all register values to default
D0 STS R/W 0000h Stop bit for all converter functions. This bit is self-clearing.

Table 9. Converter Function Select

C3 C2 C1 C0 FUNCTION
0 0 0 0 Touch screen scan function: X, Y, Z1, and Z2 coordinates converted and the results returned to X, Y, Z1, and Z2 data registers. Scan continues until either the pen is lifted or a stop bit is sent.
0 0 0 1 Touch screen scan function: X and Y coordinates converted and the results returned to X and Y data registers. Scan continues until either the pen is lifted or a stop bit is sent.
0 0 1 0 Touch screen scan function: X coordinate converted and the results returned to X data register.
0 0 1 1 Touch screen scan function: Y coordinate converted and the results returned to Y data register.
0 1 0 0 Touch screen scan function: Z1 and Z2 coordinates converted and the results returned to Z1 and Z2 data registers.
0 1 0 1 Auxiliary input converted and the results returned to the AUX data register.
0 1 1 0 A temperature measurement is made and the results returned to the Temperature Measurement 1 data register.
0 1 1 1 A differential temperature measurement is made and the results returned to the Temperature Measurement 2 data register.
1 0 0 0 Auxiliary input is converted continuously and the results returned to the AUX data register.
1 0 0 1 Touch screen panel connection to X-axis drivers is tested. The test result is output to PINTDAV and shown in STATUS register.
1 0 1 0 Touch screen panel connection to Y-axis drivers is tested. The test result is output to PINTDAV and shown in STATUS register.
1 0 1 1 RESERVED (Note: any condition caused by this command can be cleared by setting the STS bit to 1).
1 1 0 0 Touch screen panel short-circuit (between X and Y plates) is tested through Y-axis. The test result is output to PINTDAV and shown in the STATUS register.
1 1 0 1 X+, X– drivers status
1 1 1 0 Y+, Y– drivers status
1 1 1 1 Y+, X– drivers status

Touch Screen Scan Function for XYZ or XY

C3-C0 = 0000 or 0001

These scan functions can collaborate with the PSM bit that defines the control mode of converter functions. If the PSM bit is set to '1', these scan function select commands are recommended to be issued before a pen touch is detected in order to allow the TSC2014 to initiate and control the scan processes immediately after the screen is touched. If these functions are not issued before a pen touch is detected, the TSC2014 waits for the host to write these functions before starting a scan process. If PSM stays as '1' after a TSC-initiated scan function is complete, the host is not required to write these function select bits again for each of the following pen touches after the detected touch. In the host-controlled converter function mode (PSM = 0), the host must send these functions select bits repeatedly for each scan function after a detected pen touch.

Note that the data registers may be updated while a host reading is in progress. Using the sequential read cycle (see Figure 34) prevents the TSC from updating registers while a host reading is in progress. To ensure that the XYZ or XY coordinates are correctly read, use the sequential read cycle to read the coordinates after the scan.

Touch Screen Sensor Connection Tests for X-Axis and Y-Axis

Range of resistances of different touch screen panels can be selected by setting the TBM bits in CFR1; see Table 18. Once the resistance of the sensor panel is selected, two continuity tests are run separately for the X-axis and Y-axis. The unit under test must pass both connection tests to ensure that a proper connection is secured.

C3-C0 = 1001

PINTDAV = 0 during this connection test. A '1' shown at end of the test indicates the X-axis drivers are well-connected to the sensor; otherwise, X-axis drivers are poorly connected. If drivers fail to connect, then PINTDAV stays low until a stop bit (STS set to '1') is issued.

C3-C0 = 1010

PINTDAV = 0 during this connection test. A '1' shown at end of the test indicates the Y-axis drivers are well-connected to the sensor; otherwise, Y-axis drivers are poorly connected. If the drivers are fail to connect, then PINTDAV stays low until a stop bit (STS set to '1') is issued.

Touch Sensor Short-Circuit Test

If the TBM bits of CFR1 detailed in Table 18 are all set to '1', a short-circuit in the touch sensor can be detected.

C3-C0 = 1011

Reserved.

C3-C0 = 1100

PINTDAV = 0 during this short-circuit test. A '1' shown at end of the test indicates there is no short-circuit detected (through Y-axis) between the flex and stable layers. If there is a short-circuit detected, PINTDAV stays low until a stop bit (STS set to '1') is issued.

RM

Resolution select. If RM = 1, the conversion result resolution is 12-bit; otherwise, the resolution is 10-bit. This bit is the same RM bit shown in CFR0.

SWRST

Software reset input. All register values are set to default value if a '1' is written to this bit. This bit is automatically set to '0' in order to cancel the software reset and resume normal operation.

STS

Stop bit for all converter functions. When writing a '1' to this register, this bit aborts the converter function currently running in the TSC2014. A '0' is automatically written to this register in order to end the stop bit. This bit can only stop converter functions; it does not reset any data, status, or configuration registers. This bit is the same STS bit shown in CFR0, but can only be read through the CFR0 register with different interpretations.

Table 10. STS Bit Operation

OPERATION VALUE DESCRIPTION
Write 0 Normal operation
Write 1 Stop converter functions and power down

Communication Protocol

The TSC2014 is controlled entirely by registers. Reading and writing to these registers are accomplished by the use of Control Byte 0, which includes a 4-bit address plus one read/write TSC register control bit. The data registers defined in Table 7 are all 16-bit, right-adjusted.

NOTE

Except for some configuration registers and the Status register that are full 16-bit registers, the rest of the value registers are 12-bit (or 10-bit) data preceded by four (or six) zeros.

Configuration Register 0

Figure 39. Configuration Register 0 (Reset Value = 4000h for Read; 0000h for Write)
MSB
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
D0
PSM STS RM CL1 CL0 PV2 PV1 PV0 PR2 PR1 PR0 SN2 SN1 SN0 DTW LSM

PSM

Pen status/control mode. Reading this bit allows the host to determine if the screen is touched. Writing to this bit selects the mode used to control the flow of converter functions that are either initiated and/or controlled by host or under control of the TSC2014 responding to a pen touch. When reading, the PSM bit indicates if the pen is down or not. When writing to this register, this bit determines if the TSC2014 controls the converter functions, or if the converter functions are host-controlled. The default state is the host-controlled converter function mode (0). The other state (1) is the TSC-initiated scan function mode that must only collaborate with C3-C0 = 0000 or 0001 in order to allow the TSC2014 to initiate and control the scan function for XYZ or XY when a pen touch is detected.

Table 11. PSM Bit Operation

OPERATION VALUE DESCRIPTION
Read 0 No screen touch detected
Read 1 Screen touch detected
Write 0 Converter functions initiated and/or controlled by host
Write 1 Converter functions initiated and controlled by the TSC2014

STS

A/D converter status. When reading, this bit indicates if the converter is busy or not busy. Continuous scans or conversions can be stopped by writing a '1' to this bit, immediately aborting the running converter function (even if the pen is still down) and causing the A/D converter to power down. The default state for write is 0 (normal operation), and the default state for read is 1 (converter is not busy). NOTE: The same bit can be written through Control Byte 1. This bit is self-clearing.

Table 12. STS Bit Operation

OPERATION VALUE DESCRIPTION
Read 0 Converter is busy
Read 1 Converter is not busy
Write 0 Normal operation
Write 1 Stop converter function and power down

RM

Resolution control. The A/D converter resolution is specified with this bit. See Table 13 for a description of these bits. This bit is the same whether reading or writing, and defaults to 0. Note that the same bit can be written through Control Byte 1.

Table 13. A/D Converter Resolution Control

RM FUNCTION
0 10-bit resolution. Power-up and reset default.
1 12-bit resolution

CL1, CL0

Conversion clock control. These two bits specify the clock rate that the A/D converter uses to perform conversion, as shown in Table 14.

Table 14. A/D Converter Conversion Clock Control

CL1 CL0 FUNCTION
0 0 fADC = fOSC/1. This is referred to as the 4MHz A/D converter clock rate, 10-bit resolution only(1).
0 1 fADC = fOSC/2. This is referred to as the 2MHz A/D converter clock rate.
1 0 fADC = fOSC/4. This is referred to as the 1MHz A/D converter clock rate.
1 1 fADC = fOSC/4. This is referred to as the 1MHz A/D converter clock rate.
For VDD = 1.2V at –40°C, a lower A/D converter clock rate should be used to allow enough time for conversion settling.

PV2-PV0

Panel voltage stabilization time control. These bits specify a delay time from the moment the touch screen drivers are enabled to the time the voltage is sampled and a conversion is started. These bits allow the user to adjust the appropriate settling time for the touch panel and external capacitances. See Table 15 for settings of these bits. The default state is 000, indicating a 0μs stabilization time. These bits are the same whether reading or writing.

Table 15. Panel Voltage Stabilization Time Control

PV2 PV1 PV0 STABILIZATION TIME (tPVS)
0 0 0 0μs
0 0 1 100μs
0 1 0 500μs
0 1 1 1ms
1 0 0 5ms
1 0 1 10ms
1 1 0 50ms
1 1 1 100ms

PR2-PR0

Precharge time selection. These bits set the amount of time allowed for precharging any pin capacitance on the touch screen prior to sensing if a pen touch is happening.

Table 16. Precharge Time Selection

PR2 PR1 PR0 PRECHARGE TIME(tPRE)
0 0 0 20μs
0 0 1 84μs
0 1 0 276μs
0 1 1 340μs
1 0 0 1.044ms
1 0 1 1.108ms
1 1 0 1.300ms
1 1 1 1.364ms

SNS2-SNS0

Sense time selection. These bits set the amount of time the TSC2014 waits to sense whether the screen is touched after converting a coordinate.

Table 17. Sense Time Selection

SNS2 SNS1 SNS0 SENSE TIME (tSNS)
0 0 0 32μs
0 0 1 96μs
0 1 0 544μs
0 1 1 608μs
1 0 0 2.080ms
1 0 1 2.144ms
1 1 0 2.592ms
1 1 1 2.656ms

DTW

Detection of pen touch in wait (patent pending). Writing a '1' to this bit enables the pen touch detection in the background while waiting for the host to issue the converter function in host-initiated/controlled modes. This background detection allows the TSC2014 to pull high at PINTDAV to indicate no pen touch detected while waiting for the host to issue the converter function. If the host polls a high state at PINTDAV before the convert function is sent, the host can abort the issuance of the convert function and stay in the polling PINTDAV mode until the next pen touch is detected.

LSM

Longer sampling mode. When this bit is set to '1', the extra 500ns of sampling time is added to the normal sampling cycles of each conversion. This additional time is represented as approximately two internal oscillator clock cycles. For VDD = 1.2V at –40°C, the LSM bit should be set to '1' so that the sampled signal has enough time to settle.

Configuration Register 1

Configuration register 1 (CFR1) defines the connection test-bit modes configuration and batch delay selection.

Figure 40. Configuration Register 1 (Reset Value = 0000h)
MSB
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
D0
Resrvd Resrvd Resrvd Resrvd TBM3 TBM2 TBM1 TBM0 Resrvd Resrvd Resrvd Resrvd Resrvd BTD2 BTD1 BTD0

TBM3-TBM0

Connection test-bit modes (patent pending). These bits specify the mode of test bits used for the predefined range of the combined X-axis and Y-axis touch screen panel resistance (RTS).

Table 18. Touch Screen Resistance Range and Test-Bit Modes

TEST-BIT MODES RTS
(kΩ)
TBM3 TBM2 TBM1 TBM0
0 0 0 0 0.17
0 0 0 1 0.17 < RTS ≤ 0.52
0 0 1 0 0.52 < RTS ≤ 0.86
0 0 1 1 0.86 < RTS ≤ 1.6
0 1 0 0 1.6 < RTS ≤ 2.2
0 1 0 1 2.2 < RTS ≤ 3.6
0 1 1 0 3.6 < RTS ≤ 5.0
0 1 1 1 5.0 < RTS ≤ 7.8
1 0 0 0 7.8 < RTS ≤ 10.5
1 0 0 1 10.5 < RTS ≤ 16.0
1 0 1 0 16.0 < RTS ≤ 21.6
1 0 1 1 21.6 < RTS ≤ 32.6
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Only for short-circuit panel test

BTD2-BTD0

Batch Time Delay mode. These are the selection bits that specify the delay before a sample/conversion scan cycle is triggered. When it is set, Batch Time Delay mode uses a set of timers to automatically trigger a sequence of sample-and-conversion events. The mode works for both TSC-initiated scans (XYZ or XY) and host-initiated scans (XYZ or XY).

A TSC-initiated scan (XYZ or XY) can be configured by setting the PSM bit in CFR0 to '1' and C[3:0] in Control Byte 1 to '0000' or '0001'. In the case of a TSC-initiated scan (XYZ or XY), the sequence begins with the TSC responding to a pen touch. After the first processed sample set completes during the batch delay, the scan enters a wait mode until the end of the batch delay is reached. If a pen touch is still detected at that moment, the scan continues to process the next sample set, and the batch delay is resumed. The throughput of the processed sample sets (shown in Table 19 as sample sets per second, or SSPS) is regulated by the selected batch delay during the time of the detected pen touch. A TSC-initiated scan (XYZ or XY) can be configured by setting the PSM bit in CFR0 to '1' and C[3:0] in Control Byte 1 to '0000' or '0001'. Note that the throughput of the processed sample set also depends on the settings of stabilization, precharge, and sense times, and the total number of samples to be processed per coordinates. If the accrual time of these factors exceeds the batch delay time, the accrual time dominates. Batch delay time starts when the pen touch initiates the scan function that converts coordinates.

A host-initiated scan (XYZ or XY) can be configured by setting the PSM bit in CFR0 to '0' and C[3:0] in Control Byte 1 to '0000' or '0001'. For the host-initiated scan (XYZ or XY), the host must set TSC internal register C[3:0] in Control Byte 1 to '0000' or '0001' initially after a pen touch is detected; see , in the Theory of Operation section. After the scan (XYZ or XY) is engaged, the throughput of the processed sample sets is regulated by the selected batch delay timer, as long as the initial detected touch is not interrupted.

Table 19. Touch Screen Throughput and Batch Selection Bits

BATCH DELAY SELECTION DELAY TIME
(ms)
THROUGHPUT FOR TSC-INITIATED
OR HOST-INITIATED SCAN, XYZ OR XY
(SSPS)
BTD2 BTD1 BTD0
0 0 0 0 Normal operation throughput depends on settings.
0 0 1 1 1000
0 1 0 2 500
0 1 1 4 250
1 0 0 10 100
1 0 1 20 50
1 1 0 40 25
1 1 1 100 10

For example, if stabilization time, precharge time, and sense time are selected as 100μs, 84μs, and 96μs, respectively, and the batch delay time is 2ms, then the scan function enters wait mode after the first processed sample set until the 2ms of batch delay time is reached. When the scan function starts to process the second sample set (if the screen is still touched), the batch delay restarts at 2ms (in this example). This procedure remains regulated by 2ms until the pen touch is not detected or the scan function is stopped by a stop bit or any reset form.

Configuration Register 2

Configuration register 2 (CFR2) defines the preprocessor configuration.

Figure 41. Configuration Register 2 (Reset Value = 0000h)
MSB
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
D0
PINTS1 PINTS0 M1 M0 W1 W0 TZ1 TZ0 AZ1 AZ0 Resrvd MAVE
X
MAVE
Y
MAVE
Z
MAVE
AUX
MAVE
TEMP

PINTS1 (default 0)

This bit controls the output format of the PINTDAV pin. When this bit is set to '0', the output format is shown as the AND-form of internal signals of PENIRQ and DAV). When this bit is set to '1', PINTDAV outputs PENIRQ only.

PINTS0 (default 0)

This bit selects what is output on the PINTDAV pin. If this bit set to '0', the output format of PINTDAV depends on the selection made on the PINTS1 bit. If this bit set to '1', the internal signal of DAV is output on PINTDAV.

Table 20. PINTSx Selection

PINTS1 PINTS0 PINTDAV PIN OUTPUT =
0 0 AND combination of PENIRQ (active low) and DAV (active high).
0 1 Data available, DAV (active low).
1 0 Interrupt, PENIRQ (active low) generated by pen-touch.
1 1 Data available, DAV (active low).

M1, M0, W1, W0 (default 0000)

Preprocessing MAV filter control. Note that when the MAV filter is processing data, the STS bit and the corresponding DAV bits in the status register indicate that the converter is busy until all conversions necessary for the preprocessing are complete. The default state for these bits is 0000, which bypasses the preprocessor. These bits are the same whether reading or writing.

TZ1 and TZ0, or AZ1 and AZ0 (default 00)

Zone detection bit definition (for TEMP or AUX measurements). TZ1 and TZ0 are for the TEMP measurement. AZ1 and AZ0 are for the AUX measurement. The action taken in zone detection is to store the processed data in the corresponding data registers and to update the corresponding DAV bits in status register. If the processed data do not meet the selected criteria, these data are ignored and the corresponding DAV bits are not updated. When zone detection is disabled, the processed data are simply stored in the corresponding data registers and the corresponding DAV bits are updated without any comparison of criteria. Note that the converted samples are always processed according to the setting of the MAVE bits for AUX/TEMP before zone detection takes effect. See Table 24 for thresholds.

Table 21. Zone Detection Bit Definition

TZ1/AZ1 TZ0/AZ0 FUNCTION
0 0 Zone detection is disabled.
0 1 When the processed data are below low threshold
1 0 When the processed data are between low and high thresholds
1 1 When the processed data are above high threshold

MAVE (default is 00000)

MAV filter function enable bit. When the corresponding bit is set to '1', the MAV filter setup is applied to the corresponding measurement.

Converter Function Select Register

The Converter Function Select (CFN) register reflects the converter function select status.

Figure 42. Converter Function Select Status Register (Reset Value = 0000h)
MSB
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
D0
CFN15 CFN14 CFN13 CFN12 CFN11 CFN10 CFN9 CFN8 CFN7 CFN6 CFN5 CFN4 CFN3 CFN2 CFN1 CFN0

CFN15-CFN13

Touch screen drivers status. These bits represent the current status of the touch screen drivers that are turned on. CFN13 is set to '1' if both X+ and X- drivers are turned on. CFN14 is set to '1' if both Y+ and Y- drivers are turned on. CFN15 is set to '1' if Y+ and X- drivers are turned on. Otherwise, these bits are set to '0'. These bits are reset to 0h whenever the converter function is either complete, stopped by the STS bit, or reset (by a hardware reset from the RESET pin or a software reset from SWRST bit in Control Byte 1).

CFN12-CFN0

Converter function select status. These bits represent the converter function currently running, which is set in bits C3-C0 of Control Byte 1. When the CFNx bit shows '1', where x is the decimal value of converter function select bits C3-C0, it indicates that the converter function that is set in bits C3-C0 is running. For example, when CFN2 shows '1', it indicates the converter function set in bits C3-C0 ('0010') is running. The CFNx bits are reset to 0000h whenever the converter function is complete, stopped by STS bit, or reset (by the hardware reset from the RESET pin or the software reset from SWRST bit in Control Byte 1). However, if the TSC-initiated scan function mode is issued (by setting the PSM bit in the CFR0 register to '1'), the CFN0 or CFN1 bit will not be reset when the corresponding converter function is complete because there is no pen touch. This event allows the TSC2014 to immediately initiate the scan process (corresponding to CFN0 or CFN1 set to '1') when the next pen touch is detected.

Figure 43. STATUS Register (Reset Value = 0004h)
MSB
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
D0
DAV
Due
X
DAV
Due
Y
DAV
Due
Z1
DAV
Due
Z2
DAV
Due
AUX
DAV
Due
TEMP1
DAV
Due
TEMP2
RESRVD
(read '0')
RESET
Flag
X
CON
Y
CON
RESRVD
(read '0')
Y
SHR
PDST ID1 ID0

DAV Bits

Data available bits. These seven bits mirror the operation of the internal signals of DAV. When any processed data are stored in data registers, the corresponding DAV bit is set to '1'. It stays at '1' until the register(s) updated to the processed data have been read out by the host.

Table 22. DAV Function

DAV DESCRIPTION
0 No new processed data are available.
1 Processed data are available. This will stay at 1 until the host has read out all updated registers.

RESET Flag

See Table 23 for the interpretation of the RESET flag bits.

Table 23. RESET Flag Bits

RESET Flag DESCRIPTION
0 Device was reset since last status poll (hardware or software reset).
1 Device has not been reset since last status poll.

X CON

This bit is '1' if the X axis of the touch screen panel is properly connected to the X drivers. This bit is the connection test result.

Y CON

This bit is '1' if the Y axis of the touch screen panel is properly connected to the Y drivers. This bit is the connection test result.

Y SHR

This bit is '1' if there is no short-circuit tested at the Y axis of the touch screen panel. This bit is the short-circuit test result.

PDST

Power down status. This bit reflects the setting of the PND0 bit in Control Byte 0. When this bit shows '0', it indicates A/D converter bias circuitry is still powered on after each conversion and before the next sampling; otherwise, it indicates A/D converter bias circuitry is powered down after each conversion and before the next sampling. However, it is powered down between conversion sets. Because this status bit is synchronized with the internal clock, it does not reflect the setting of the PND0 bit until a pen touch is detected or a converter function is running.

ID[1:0]

Device ID bits: These bits represent the version ID of TSC2014. This version defaults to '00'.

Data Registers

The data registers of the TSC2014 hold data results from conversions. All of these registers default to 0000h upon reset.

X, Y, Z1, Z2, AUX, TEMP1 and TEMP2 Registers

The results of all A/D conversions are placed in the appropriate data registers, as described in Table 7. The data format of the result word (R) of these registers is right-justified, as shown in Figure 44.

The data registers of the TSC2014 hold data results from conversions. All of these registers default to 0000h upon reset.

Figure 44. Internal Register Format
MSB
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
D0
0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

The TSC2014 has several 16-bit registers that allow control of the device, as well as providing a location to store results from the TSC2014 until read out by the host microprocessor. Table 24 shows the memory map.

Table 24. Register Content and Reset Values(1)

A3-A0
(HEX)
REGISTER
NAME
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RESET
VALUE
(HEX)
0 X 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
1 Y 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
2 Z1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
3 Z2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
4 AUX 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
5 Temp1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
6 Temp2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
7 Status S15 S14 S13 S12 S11 S10 S9 0 S7 S6 S5 Rsvd
(2)
S3 S2 S1 S0 0004
8 AUX High 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0FFF
9 AUX Low 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
A Temp High 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0FFF
B Temp Low 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
C CFR0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 4000
D CFR1 0 0 0 0 R11 R10 R9 R8 0 0 0 0 0 R2 R1 R0 0000
E CFR2 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 0 R4 R3 R2 R1 R0 0000
F Converter Function Select Status R15 R14 R13 R12 Rsvd
(2)
R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
For all combination bits, the pattern marked as Rsvd (reserved) must not be used. The default pattern is read back after reset.
This bit is reserved.