SLLSFB2A April 2020 – June 2026 TUSB1146
PRODUCTION DATA
Each of the TUSB1146 receiver lanes has individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. details the gain value for each available combination when TUSB1146 is in GPIO mode. These same options are also available in I2C mode by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL, EQ2_SEL, and SSEQ_SEL.
| Register(s): EQ1_SEL or EQ2_SEL Equalization Setting # | EQ1 PIN Level | EQ0 PIN Level | EQ Gain at 5 GHz minus Gain at 100MHz (dB) |
|---|---|---|---|
| 0 | 0 | 0 | -0.7 |
| 1 | 0 | R | 1.1 |
| 2 | 0 | F | 2.7 |
| 3 | 0 | 1 | 4.5 |
| 4 | R | 0 | 5.5 |
| 5 | R | R | 6 |
| 6 | R | F | 7.5 |
| 7 | R | 1 | 8.0 |
| 8 | F | 0 | 8.5 |
| 9 | F | R | 9.0 |
| 10 | F | F | 9.3 |
| 11 | F | 1 | 9.8 |
| 12 | 1 | 0 | 10.0 |
| 13 | 1 | R | 10.3 |
| 14 | 1 | F | 10.7 |
| 15 | 1 | 1 | 11 |
| Register(s): SSEQ_SEL Equalization Setting # | SSEQ1 PIN LEVEL | SSEQ0 PIN LEVEL | EQ Gain at 5 GHz minus Gain at 100MHz (dB) |
|---|---|---|---|
| 0 | 0 | 0 | -0.5 |
| 1 | 0 | R | 1.5 |
| 2 | 0 | F | 3.1 |
| 3 | 0 | 1 | 4.5 |
| 4 | R | 0 | 5.5 |
| 5 | R | R | 6.5 |
| 6 | R | F | 7.5 |
| 7 | R | 1 | 8.7 |
| 8 | F | 0 | 9.0 |
| 9 | F | R | 9.4 |
| 10 | F | F | 9.8 |
| 11 | F | 1 | 10.2 |
| 12 | 1 | 0 | 10.5 |
| 13 | 1 | R | 10.7 |
| 14 | 1 | F | 11.0 |
| 15 | 1 | 1 | 11.5 |
| Register(s): DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, or DP3EQ_SEL Equalization Setting # | DPEQ1 PIN LEVEL | DPEQ0 PIN LEVEL | EQ Gain at 4.05 GHz minus Gain at 100MHz (dB) |
|---|---|---|---|
| 0 | 0 | 0 | 0.8 |
| 1 | 0 | R | 1.3 |
| 2 | 0 | F | 2.8 |
| 3 | 0 | 1 | 4.1 |
| 4 | R | 0 | 5.8 |
| 5 | R | R | 6.2 |
| 6 | R | F | 7.1 |
| 7 | R | 1 | 7.9 |
| 8 | F | 0 | 8.6 |
| 9 | F | R | 9.2 |
| 10 | F | F | 9.8 |
| 11 | F | 1 | 10.3 |
| 12 | 1 | 0 | 10.7 |
| 13 | 1 | R | 11.2 |
| 14 | 1 | F | 11.5 |
| 15 | 1 | 1 | 12 |