SLLSEZ6D February   2019  – December 2023 TUSB216

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-Speed Boost
      2. 7.3.2 RX Sensitivity
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low-Speed (LS) Mode
      2. 7.4.2 Full-Speed (FS) Mode
      3. 7.4.3 High-Speed (HS) Mode
      4. 7.4.4 High-Speed Downstream Port Electrical Compliance Test Mode
      5. 7.4.5 Shutdown Mode
      6. 7.4.6 I2C Mode
      7. 7.4.7 BC 1.2 Battery Charging Controller
    5. 7.5 TUSB216 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Test Procedure to Construct USB High-speed Eye Diagram
          1. 8.2.2.1.1 For a Host Side Application
          2. 8.2.2.1.2 For a Device Side Application
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RWB|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 TUSB216 Registers

Table 7-3 lists the memory-mapped registers for the TUSB216 registers. All register offset addresses not listed in Table 7-3 should be considered as reserved locations and the register contents should not be modified.

Table 7-3 TUSB216 Registers
OffsetAcronymRegister NameSection
0x1EDGE_BOOSTThis register is setting EDGE BOOST level.Go
0x3CONFIGURATIONThis register is selecting device mode.Go
0xEDC_BOOSTThis register is setting DC BOOST level.Go
0x25RX_SENThis register is setting RX Sensitivity level.Go

Complex bit access types are encoded to fit into small table cells. Table 7-4 shows the codes that are used for access types in this section.

Table 7-4 TUSB216 Access Type Codes
Access TypeCodeDescription
Read Type
RHH
R		Set or cleared by hardware
Read
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.5.1 EDGE_BOOST Register (Offset = 0x1) [reset = X]

EDGE_BOOST is shown in Figure 7-1 and described in Table 7-5.

Return to Summary Table.

This register is setting EDGE BOOST level.

Figure 7-1 EDGE_BOOST Register
76543210
ACB_LVLRESERVED
RH/W-XRH/W-X
Table 7-5 EDGE_BOOST Register Field Descriptions
BitFieldTypeResetDescription
7-4ACB_LVLRH/WX

XXXXb (sampled at startup from BOOST pin)
0000b to 1111b range

0x0 = BOOST PIN LEVEL 0 (lowest edge boost setting)

0x3 = BOOST PIN LEVEL 1

0x6 = BOOST PIN LEVEL 2

0xA = BOOST PIN LEVEL 3

0xF = (highest edge boost setting)

3-0RESERVEDRH/WX

These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these reserved bits and rewrite with the same values

7.5.2 CONFIGURATION Register (Offset = 0x3) [reset = X]

CONFIGURATION is shown in Figure 7-2 and described in Table 7-6.

Return to Summary Table.

This register is selecting device mode.

Figure 7-2 CONFIGURATION Register
7 6 5 4 3 2 1 0
RESERVED CFG_ACTIVE
RH/W-X RH/W-0x1
Table 7-6 CONFIGURATION Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED RH/W X

These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these reserved bits and rewrite with the same values
0 CFG_ACTIVE RH/W 0x1

Configuration mode
After reset, if I2C mode is true (SCL and SDA are both pulled high) set the bit to get into configuration mode and clear to return to normal mode.

0x0 = NORMAL MODE

0x1 = CONFIGURATION MODE

7.5.3 DC_BOOST Register (Offset = 0xE) [reset = X]

DC_BOOST is shown in Figure 7-3 and described in Table 7-7.

Return to Summary Table.

This register is setting DC BOOST level.

Figure 7-3 DC_BOOST Register
76543210
RESERVEDDCB_LVL
RH/W-XRH/W-X
Table 7-7 DC_BOOST Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDRH/WX

These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these reserved bits and rewrite with the same values

3-0DCB_LVLRH/WX

XXXXb (sampled at startup from BOOST pin)
0000b to 1111b range

0x0 = BOOST PIN LEVEL 0 (lowest dc boost setting)

0x2 = BOOST PIN LEVEL 1 and 2

0x6 = BOOST PIN LEVEL 3

0xF = (highest dc boost setting)

7.5.4 RX_SEN Register (Offset = 0x25) [reset = X]

RX_SEN is shown in Figure 7-4 and described in Table 7-8.

Return to Summary Table.

This register is setting RX Sensitivity level.

Figure 7-4 RX_SEN Register
76543210
RX_SEN
RH/W-X
Table 7-8 RX_SEN Register Field Descriptions
BitFieldTypeResetDescription
7-0RX_SENRH/WX

XXXXb (sampled at startup from RX_SEN pin)
00000000b to 11111111b range

0x0 = RX_SEN LEVEL LOW

0x33 = RX_SEN LEVEL MID

0x66 = RX_SEN LEVEL HIGH

0xFF = (highest setting)