SLLSFK6 September   2021 TUSB217A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High-Speed Boost
      2. 8.3.2 RX Sensitivity
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Speed (LS) Mode
      2. 8.4.2 Full-Speed (FS) Mode
      3. 8.4.3 High-Speed (HS) Mode
      4. 8.4.4 High-Speed Downstream Port Electrical Compliance Test Mode
      5. 8.4.5 Shutdown Mode
      6. 8.4.6 I2C Mode
      7. 8.4.7 BC 1.2 Battery Charging Controller
    5. 8.5 TUSB217A-Q1 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Test Procedure to Construct USB High-speed Eye Diagram
          1. 9.2.2.1.1 For a Host Side Application
          2. 9.2.2.1.2 For a Device Side Application
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 TUSB217A-Q1 Registers

Table 8-3 lists the memory-mapped registers for the TUSB217A-Q1 registers. All register offset addresses not listed in Table 8-3 should be considered as reserved locations and the register contents should not be modified.

Table 8-3 TUSB217A-Q1 Registers
Offset Acronym Register Name Section
0x1 EDGE_BOOST This register is setting EDGE BOOST level. Go
0x3 CONFIGURATION This register is selecting device mode. Go
0xE DC_BOOST This register is setting DC BOOST level. Go
0x25 RX_SEN This register is setting RX Sensitivity level. Go

Complex bit access types are encoded to fit into small table cells. Table 8-4 shows the codes that are used for access types in this section.

Table 8-4 TUSB217A-Q1 Access Type Codes
Access Type Code Description
Read Type
RH H
R		 Set or cleared by hardware
Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

8.5.1 EDGE_BOOST Register (Offset = 0x1) [reset = X]

EDGE_BOOST is shown in Figure 8-1 and described in Table 8-5.

Return to Summary Table.

This register is setting EDGE BOOST level.

Figure 8-1 EDGE_BOOST Register
7 6 5 4 3 2 1 0
ACB_LVL RESERVED
RH/W-X RH/W-X
Table 8-5 EDGE_BOOST Register Field Descriptions
Bit Field Type Reset Description
7-4 ACB_LVL RH/W X

XXXXb (sampled at startup from BOOST pin)
0000b to 1111b range

0x0 = BOOST PIN LEVEL 0 (lowest edge boost setting)

0x3 = BOOST PIN LEVEL 1

0x6 = BOOST PIN LEVEL 2

0xA = BOOST PIN LEVEL 3

0xF = (highest edge boost setting)
3-0 RESERVED RH/W X

These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these reserved bits and rewrite with the same values

8.5.2 CONFIGURATION Register (Offset = 0x3) [reset = X]

CONFIGURATION is shown in Figure 8-2 and described in Table 8-6.

Return to Summary Table.

This register is selecting device mode.

Figure 8-2 CONFIGURATION Register
7 6 5 4 3 2 1 0
RESERVED CFG_ACTIVE
RH/W-X RH/W-0x1
Table 8-6 CONFIGURATION Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED RH/W X

These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these reserved bits and rewrite with the same values
0 CFG_ACTIVE RH/W 0x1

Configuration mode
After reset, if I2C mode is true (SCL and SDA are both pulled high) set the bit to get into configuration mode and clear to return to normal mode.

0x0 = NORMAL MODE

0x1 = CONFIGURATION MODE

8.5.3 DC_BOOST Register (Offset = 0xE) [reset = X]

DC_BOOST is shown in Figure 8-3 and described in Table 8-7.

Return to Summary Table.

This register is setting DC BOOST level.

Figure 8-3 DC_BOOST Register
7 6 5 4 3 2 1 0
RESERVED DCB_LVL
RH/W-X RH/W-X
Table 8-7 DC_BOOST Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED RH/W X

These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these reserved bits and rewrite with the same values
3-0 DCB_LVL RH/W X

XXXXb (sampled at startup from BOOST pin)
0000b to 1111b range

0x0 = BOOST PIN LEVEL 0 (lowest dc boost setting)

0x2 = BOOST PIN LEVEL 1 and 2

0x6 = BOOST PIN LEVEL 3

0xF = (highest dc boost setting)

8.5.4 RX_SEN Register (Offset = 0x25) [reset = X]

RX_SEN is shown in Figure 8-4 and described in Table 8-8.

Return to Summary Table.

This register is setting RX Sensitivity level.

Figure 8-4 RX_SEN Register
7 6 5 4 3 2 1 0
RX_SEN
RH/W-X
Table 8-8 RX_SEN Register Field Descriptions
Bit Field Type Reset Description
7-0 RX_SEN RH/W X

XXXXb (sampled at startup from RX_SEN pin)
00000000b to 11111111b range

0x0 = RX_SEN LEVEL LOW

0x33 = RX_SEN LEVEL MID

0x66 = RX_SEN LEVEL HIGH

0xFF = (highest setting)