SLUSDD4B April   2019  – December 2020 UC1843B-SP


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO
      2. 7.3.2 Reference
      3. 7.3.3 Totem-Pole Output
    4. 7.4 Device Functional Modes
  8. Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Switching Frequency
        2. Transformer
        3. RCD Diode Clamp
        4. Output Diode
        5. Output Filter and Capacitor
        6. Compensation
        7. Sense Resistor and Slope Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Feedback Traces
      2. 10.1.2 Input/Output Capacitors
      3. 10.1.3 Compensation Components
      4. 10.1.4 Traces and Ground Planes
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Output Filter and Capacitor

The output capacitance value is picked such that there is enough capacitance for the required voltage ripple and output current load step. The UC1843B-SP design uses equations Equation 22 and Equation 24 to find a minimum capacitance.

Equation 22. Cout>Iout×DMAXVRipple×fosc
Equation 23. Cout>10 A×0.550 mV×200 kHz=500 μF
Equation 24. Cout>ΔIstep2π×ΔVout×fco
Equation 25. Cout>10 A2π×0.7 V×2.2 kHz=1 mF

A value of around 1145 µF was chosen to keep output voltage ripple low. Note that the output voltage ripple in the design was further decreased by adding an output filter and by adding an inductor after a small portion of the output capacitance. Six ceramic capacitors were picked to be placed before the output filter and then the large tantalum capacitors with some small ceramics were added to be part of the output filter. The initial ceramics will help with the initial current ripple, but have a very large output voltage ripple. This voltage ripple will be attenuated by the inductor and capacitor combination placed between the ceramic capacitors and the output. The equations below allow for finding the amount of attenuation that will come from a specific output filter inductance. An inductance of 500 nH was chosen to attenuate the output voltage ripple and the attenuation was sufficient for the design.

Equation 26. Fresonant=12π×LFilter×CoBulk
Equation 27. Fresonant=12π×0.5 nH×1127 μF=6.7 kHz
Equation 28. FZero=12π×CoBulk×ESRoBulk
Equation 29. FZero=12π×1127 μF×0.009 Ω=15.69 kHz
Equation 30. Attenuationfsw=40×log10foscfresonant-20×log10foscfzero
Equation 31. Attenuationfsw=40×log10200 kHz6.7 kHz-20×log10200 kHz15.69 kHz =36.88 dB

Sometimes the output filter can cause peaking at high frequencies, this can be damped by adding a resistor in parallel with the inductor. For the UC1843B-SP design, 0.5 Ω was used as a very conservative value. The resistance needed to damp the peaking can be calculated using the following equations:

Equation 32. ωo=2(CoCerm+CoBulk)LFilter×CoCerm×CoBulk
Equation 33. ωo=2(19 μF+1127 μF)500 nH×19 μF×1127 μF=463 kHz
Equation 34. RFilter=Ro×LFilter×(CoCerm+CoBulk)-LFilterωoRo×(CoCerm+CoBulk)ωo-LFilter×CoCerm
Equation 35. RFilter=0.5×500 nH×(19 μF+1127 μF)-500 nH463 kHz0.5×(19 μF+1127 μF)463 kHz-500 nH×19 μF=0.232 Ω