SLUSDA5 February   2018 UCC21222-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Thermal Derating Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Minimum Pulses
    2. 7.2 Propagation Delay and Pulse Width Distortion
    3. 7.3 Rising and Falling Time
    4. 7.4 Input and Disable Response Time
    5. 7.5 Programmable Dead Time
    6. 7.6 Power-up UVLO Delay to OUTPUT
    7. 7.7 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in the UCC21222-Q1
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 DT Pin Tied to VCCI or DT Pin Left Open
        2. 8.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Designing INA/INB Input Filter
        3. 9.2.2.3 Select Dead Time Resistor and Capacitor
        4. 9.2.2.4 Select External Bootstrap Diode and its Series Resistor
        5. 9.2.2.5 Gate Driver Output Resistor
        6. 9.2.2.6 Estimating Gate Driver Power Loss
        7. 9.2.2.7 Estimating Junction Temperature
        8. 9.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.8.1 Selecting a VCCI Capacitor
          2. 9.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.8.3 Select a VDDB Capacitor
        9. 9.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • AEC Q100 Qualified with:
    • Device Temperature Grade 1
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C6
  • Junction Temperature Range –40°C to 150°C
  • Resistor-Programmable Dead Time
  • Universal: Dual Low-Side, Dual High-Side or Half-Bridge Driver
  • 4-A Peak Source, 6-A Peak Sink Output
  • 3-V to 5.5-V Input VCCI Range
  • Up to 18-V VDD Output Drive Supply
    • 8-V VDD UVLO
  • Switching Parameters:
    • 28-ns Typical Propagation Delay
    • 10-ns Minimum Pulse Width
    • 5-ns Maximum Delay Matching
    • 5.5-ns Maximum Pulse-Width Distortion
  • TTL and CMOS Compatible Inputs
  • Integrated Deglitch Filter
  • I/Os withstand –2-V for 200 ns
  • Common-Mode Transient Immunity (CMTI) Greater than 100-V/ns
  • Isolation Barrier Life >40 Years
  • Surge Immunity up to 7800-VPK
  • Narrow Body SOIC-16 (D) Package
  • Safety-Related Certifications (Planned):
    • 4242-VPK Isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
    • 3000-VRMS Isolation for 1 Minute per UL 1577
    • CSA Certification per IEC 60950-1, IEC 62368-1 and IEC 61010-1 End Equipment Standards
    • CQC Certification per GB4943.1-2011