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UCC21222-Q1

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Automotive 3.0kVrms, 4A/6A 2-channel isolated gate driver w/ disable, programmable deadtime, 8V UVLO

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Data sheet

UCC21222-Q1

ACTIVE
Data sheet Order now

Product details

Number of channels (#) 2 Isolation rating (Vrms) 3000 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 6 DIN V VDE V 0884-10 transient overvoltage rating (Vpk) 4242 DIN V VDE V 0884-10 working voltage (Vpk) 990 Output VCC/VDD (Max) (V) 18 Output VCC/VDD (Min) (V) 9.2 Input VCC (Min) (V) 3 Input VCC (Max) (V) 5.5 Prop delay (ns) 25 Operating temperature range (C) -40 to 125 Undervoltage lockout (Typ) 8
Number of channels (#) 2 Isolation rating (Vrms) 3000 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 6 DIN V VDE V 0884-10 transient overvoltage rating (Vpk) 4242 DIN V VDE V 0884-10 working voltage (Vpk) 990 Output VCC/VDD (Max) (V) 18 Output VCC/VDD (Min) (V) 9.2 Input VCC (Min) (V) 3 Input VCC (Max) (V) 5.5 Prop delay (ns) 25 Operating temperature range (C) -40 to 125 Undervoltage lockout (Typ) 8
SOIC (D) 16 59 mm² 9.9 x 6
  • AEC Q100 Qualified with:
    • Device Temperature Grade 1
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C6
  • Junction Temperature Range –40°C to 150°C
  • Resistor-Programmable Dead Time
  • Universal: Dual Low-Side, Dual High-Side or Half-Bridge Driver
  • 4-A Peak Source, 6-A Peak Sink Output
  • 3-V to 5.5-V Input VCCI Range
  • Up to 18-V VDD Output Drive Supply
    • 8-V VDD UVLO
  • Switching Parameters:
    • 28-ns Typical Propagation Delay
    • 10-ns Minimum Pulse Width
    • 5-ns Maximum Delay Matching
    • 5.5-ns Maximum Pulse-Width Distortion
  • TTL and CMOS Compatible Inputs
  • Integrated Deglitch Filter
  • I/Os withstand –2-V for 200 ns
  • Common-Mode Transient Immunity (CMTI) Greater than 100-V/ns
  • Isolation Barrier Life >40 Years
  • Surge Immunity up to 7800-VPK
  • Narrow Body SOIC-16 (D) Package
  • Safety-Related Certifications (Planned):
    • 4242-VPK Isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
    • 3000-VRMS Isolation for 1 Minute per UL 1577
    • CSA Certification per IEC 60950-1, IEC 62368-1 and IEC 61010-1 End Equipment Standards
    • CQC Certification per GB4943.1-2011
  • AEC Q100 Qualified with:
    • Device Temperature Grade 1
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C6
  • Junction Temperature Range –40°C to 150°C
  • Resistor-Programmable Dead Time
  • Universal: Dual Low-Side, Dual High-Side or Half-Bridge Driver
  • 4-A Peak Source, 6-A Peak Sink Output
  • 3-V to 5.5-V Input VCCI Range
  • Up to 18-V VDD Output Drive Supply
    • 8-V VDD UVLO
  • Switching Parameters:
    • 28-ns Typical Propagation Delay
    • 10-ns Minimum Pulse Width
    • 5-ns Maximum Delay Matching
    • 5.5-ns Maximum Pulse-Width Distortion
  • TTL and CMOS Compatible Inputs
  • Integrated Deglitch Filter
  • I/Os withstand –2-V for 200 ns
  • Common-Mode Transient Immunity (CMTI) Greater than 100-V/ns
  • Isolation Barrier Life >40 Years
  • Surge Immunity up to 7800-VPK
  • Narrow Body SOIC-16 (D) Package
  • Safety-Related Certifications (Planned):
    • 4242-VPK Isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
    • 3000-VRMS Isolation for 1 Minute per UL 1577
    • CSA Certification per IEC 60950-1, IEC 62368-1 and IEC 61010-1 End Equipment Standards
    • CQC Certification per GB4943.1-2011

The UCC21222-Q1 device is an isolated dual channel gate driver with programmable dead time and wide temperature range. This device exhibits consistent performance and robustness under extreme temperature conditions. It is designed with 4-A peak-source and 6-A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.

The UCC21222-Q1 device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.

The input side is isolated from the two output drivers by a 3.0-kVRMS isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI).

Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include: Disable feature to shut down both outputs simultaneously when DIS is set high, integrated deglitch filter that rejects input transients shorter than 5-ns, and negative voltage handling for up to -2-V spikes for 200-ns on input and output pins. All supplies have UVLO protection.

The UCC21222-Q1 device is an isolated dual channel gate driver with programmable dead time and wide temperature range. This device exhibits consistent performance and robustness under extreme temperature conditions. It is designed with 4-A peak-source and 6-A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.

The UCC21222-Q1 device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.

The input side is isolated from the two output drivers by a 3.0-kVRMS isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI).

Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include: Disable feature to shut down both outputs simultaneously when DIS is set high, integrated deglitch filter that rejects input transients shorter than 5-ns, and negative voltage handling for up to -2-V spikes for 200-ns on input and output pins. All supplies have UVLO protection.
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Technical documentation

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Type Title Date
* Data sheet UCC21222-Q1 Automotive 4-A, 6-A, 3.0-kVRMS Isolated Dual-Channel Gate Driver with Dead Time datasheet PDF | HTML 13 Feb 2018
Certificate VDE Certificate for Basic Isolation for DIN EN IEC 60747-17 (Rev. T) 12 Jul 2022
White paper High-Voltage Semiconductor Solutions for Meeting Isolation Requirements (Rev. A) PDF | HTML 06 Jun 2022
White paper 以可靠且經濟實惠的隔離技術解決高電壓設計難題 (Rev. A) PDF | HTML 06 Jun 2022
White paper 높 은 신뢰도와 합리적인 가격대의 절연 기술 개발과 관련한 고전압 설계 문 제의 해결.. (Rev. A) PDF | HTML 06 Jun 2022
Application note The Use and Benefits of Ferrite Beads in Gate Drive Circuits PDF | HTML 16 Dec 2021
Application note External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application note Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
Certificate UL Certification E181974 Vol 4. Sec 9 (Rev. A) 22 Jul 2019
User guide Gate Drive Voltage vs. Efficiency 25 Apr 2019
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse 19 Sep 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime 30 May 2018
Technical article Boosting efficiency for your solar inverter designs 24 May 2018
White paper Driving the future of HEV/EV with high-voltage solutions (Rev. B) 16 May 2018
Technical article How to achieve higher system robustness in DC drives, part 1: negative voltage 17 Apr 2018
Application note Isolation Glossary (Rev. A) 19 Sep 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

UCC21220EVM-009 — UCC21220 4-A, 6-A 3.0-kVRMS Isolated Dual-Channel Gate Driver Evaluation Module

UCC21220EVM-009 is designed for evaluating UCC21220, which is a 3.0-kVRMS Isolated Dual-Channel Gate Driver with 4.0-A source and 6.0-A sink peak current capability. This EVM could be served to evaluate the driver IC against its datsheet. The EVM can also be used as Driver IC component selection (...)
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Simulation model

UCC21222-Q1 PSpice Transient Model

SLUM622.ZIP (57 KB) - PSpice Model
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Simulation model

UCC21222-Q1 Unencrypted PSpice Transient Model

SLUM623.ZIP (3 KB) - PSpice Model
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

PMP22650 — GaN-based, 6.6-kW, bidirectional, onboard charger reference design

The PMP22650 reference design is a 6.6-kW, bidirectional, onboard charger. The design employs a two-phase totem pole PFC and a full-bridge CLLLC converter with synchronous rectification. The CLLLC utilizes both frequency and phase modulation to regulate the output across the required regulation (...)
Schematic: PDF
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