Automotive 4-A/6-A, 3.0-kVRMS 2-channel isolated gate driver with 8-V UVLO, programmable dead time
Product details
Parameters
Package | Pins | Size
Features
- AEC Q100 Qualified with:
- Device Temperature Grade 1
- Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C6
- Junction Temperature Range –40°C to 150°C
- Resistor-Programmable Dead Time
- Universal: Dual Low-Side, Dual High-Side or Half-Bridge Driver
- 4-A Peak Source, 6-A Peak Sink Output
- 3-V to 5.5-V Input VCCI Range
- Up to 18-V VDD Output Drive Supply
- 8-V VDD UVLO
- Switching Parameters:
- 28-ns Typical Propagation Delay
- 10-ns Minimum Pulse Width
- 5-ns Maximum Delay Matching
- 5.5-ns Maximum Pulse-Width Distortion
- TTL and CMOS Compatible Inputs
- Integrated Deglitch Filter
- I/Os withstand –2-V for 200 ns
- Common-Mode Transient Immunity (CMTI) Greater than 100-V/ns
- Isolation Barrier Life >40 Years
- Surge Immunity up to 7800-VPK
- Narrow Body SOIC-16 (D) Package
- Safety-Related Certifications (Planned):
- 4242-VPK Isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
- 3000-VRMS Isolation for 1 Minute per UL 1577
- CSA Certification per IEC 60950-1, IEC 62368-1 and IEC 61010-1 End Equipment Standards
- CQC Certification per GB4943.1-2011
All trademarks are the property of their respective owners.
Description
The UCC21222-Q1 device is an isolated dual channel gate driver with programmable dead time and wide temperature range. This device exhibits consistent performance and robustness under extreme temperature conditions. It is designed with 4-A peak-source and 6-A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.
The UCC21222-Q1 device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.
The input side is isolated from the two output drivers by a 3.0-kVRMS isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI).
Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include: Disable feature to shut down both outputs simultaneously when DIS is set high, integrated deglitch filter that rejects input transients shorter than 5-ns, and negative voltage handling for up to -2-V spikes for 200-ns on input and output pins. All supplies have UVLO protection.

Request more information
The functional safety manual and functional safety FIT rate, FMD and pin FMA report are available. Request now
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- High performance driver with input and output interface.
- Ability to test most data sheet parameters
- Ability to compare performance of various drivers with compatible pinout
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (D) | 16 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.